HS-81C55RH, HS-81C56RH
TM
Data Sheet
August 2000
File Number
3039.2
Radiation Hardened 256 x 8 CMOS RAM
The HS-81C55/56RH are radiation hardened RAM and I/O
chips fabricated using the Intersil radiation hardened Self-
Aligned Junction Isolated (SAJI) silicon gate technology.
Latch-up free operation is achieved by the use of epitaxial
starting material to eliminate the parasitic SCR effect seen in
conventional bulk CMOS devices.
The HS-81C55/56RH is intended for use with the
HS-80C85RH radiation hardened microprocessor system.
The RAM portion is designed as 2048 static cells organized
as 256 x 8. A maximum post irradiation access time of
500ns allows the HS-81C55/56RH to be used with the
HS-80C85RH CPU without any wait states. The
HS-81C55RH requires an active low chip enable while the
HS-81C56RH requires an active high chip enable. These
chips are designed for operation utilizing a single 5V power
supply.
Specifications for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed here must be used when ordering.
Detailed Electrical Specifications for these devices are
contained in SMD 5962-96766. A “hot-link” is provided
on our homepage for downloading.
http://www.intersil.com/spacedefense/space.asp
Features
• Electrically Screened to SMD # 5962-96766
• QML Qualified per MIL-PRF-38535 Requirements
• Radiation Hardened EPI-CMOS
- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)
- Transient Upset . . . . . . . . . . . . . . . . . .>1 x 10
8
rad(Si)/s
- Latch-Up Free . . . . . . . . . . . . . . . . . . >1 x 10
12
rad(Si)/s
• Electrically Equivalent to Sandia SA 3001
• Pin Compatible with Intel 8155/56
• Bus Compatible with HS-80C85RH
• Single 5V Power Supply
• Low Standby Current . . . . . . . . . . . . . . . . . . . .200µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . . . . 2mA/MHz
• Completely Static Design
• Internal Address Latches
• Two Programmable 8-Bit I/O Ports
• One Programmable 6-Bit I/O Port
• Programmable 14-Bit Binary Counter/Timer
• Multiplexed Address and Data Bus
• Self Aligned Junction Isolated (SAJI) Process
• Military Temperature Range . . . . . . . . . . . -55
o
C to 125
o
C
Ordering Information
ORDERING NUMBER
5962R9676601QXC
5962R9676601QYC
5962R9676601VXC
5962R9676601VYC
5962R9676602QXC
5962R9676602QYC
5962R9676602VXC
5962R9676602VYC
INTERNAL
MKT. NUMBER
HS1-81C55RH-8
HS9-81C55RH-8
HS1-81C55RH-Q
HS9-81C55RH-Q
HS1-81C56RH-8
HS9-81C56RH-8
HS1-81C56RH-Q
HS9-81C56RH-Q
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
Functional Diagram
IO/M
AD0 - AD7
CE OR CE
†
ALE
RD
WR
RESET
TIMER CLK
TIMER OUT
TIMER
C
PORT C
8
PC0 - PC5
VDD (10V)
GND
256 x 8
STATIC
RAM
A
PORT A
8
PA0 - PA7
PORT B
B
8
PB0 - PB7
†
81C55RH = CE
81C56RH = CE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
|
Intersil and Design is a trademark of Intersil Corporation.
|
Copyright © Intersil Corporation 2000
HS-81C55RH, HS-81C56RH
Pin Descriptions
SYMBOL
RESET
TYPE
I
NAME AND FUNCTION
Reset:
Pulse provided by the HS-80C85RH to initialize the system (connect to HS-80C85RH RESET OUT).
Input high on this line resets the chip and initializes the three I/O ports to input mode. The width of RESET
pulse should typically be two HS-80C85RH clock cycle times.
Address/Data:
Three-state Address/Data lines that interface with the CPU lower 8-bit Address/Data Bus. The
8-bit address is latched into the address latch inside the HS-81C55 and HS-81C56RH on the falling edge of
ALE. The address can be either for the memory section or the I/O section depending on the IO/M input. The
8-bit data is either written into the chip or read from the chip, depending on the WR or RD input signal.
Chip Enable:
On the HS-81C55RH, this pin is CE and is ACTIVE LOW. On the HS-81C56RH, this pin is CE
and is ACTIVE HIGH.
Read Control:
Input low on this line with the Chip Enable active enables and AD0 - AD7 buffers. If IO/M pin
is low, the RAM content will be read out to the AD bus. Otherwise the content of the selected I/O port or
command/status registers will be read to the AD bus.
Write Control:
Input low on this line with the Chip Enable active causes the data on the Address/Data bus to
be written to the RAM or I/O ports and command/status register, depending on IO/M.
Address Latch Enable:
This control signal latches both the address on the AD0 - AD7 lines and the state of
the Chip Enable and IO/M into the chip at the falling edge of ALE.
I/O Memory:
Selects memory if low and I/O and command/status registers if high.
Port A:
These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port B:
These 8 pins are general purpose I/O pins. The in/out direction is selected by programming the
command register.
Port C:
These 6 pins can function as either input port, output port, or as control signals for PA and PB.
Programming is done through the command register. When PC0 - PC5 are used as control signals, they will
provide the following:
PC0 - A INTR (Port A Interrupt)
PC1 - ABF (Port A Buffer Full)
PC2 - A STB (Port A Strobe)
PC3 - B INTR (Port B Interrupt)
PC4 - B BF (Port B Buffer Full)
PC5 - B STB (Port B Strobe)
Timer Input:
Input to the counter-timer.
Timer Output:
This output can be either a square wave or a pulse, depending on the timer mode.
Voltage:
+5V.
Ground:
Ground reference.
AD0 - AD7
I/O
CE or CE
RD
I
I
WR
ALE
IO/M
PA0 - PA7 (8)
PB0 - PB7 (8)
PC0 - PC7 (8)
I
I
I
I/O
I/O
I/O
TIMER IN
TIMER OUT
VDD
GND
I
O
I
I
3
FPGA/CPLD
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