HS1-80C86RH/Proto datasheet, PDF

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HS1-80C86RH/Proto: Description16-Bit Microprocessor; Categoryaccessories; File Size627KB，30 Pages; ManufacturerIntersil ( Renesas ); Websitehttp://www.intersil.com/cda/home/

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HS1-80C86RH/Proto Overview

16-Bit Microprocessor

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DATASHEET

HS-80C86RH

Radiation Hardened 16-Bit CMOS Microprocessor

The Intersil HS-80C86RH high performance radiation

hardened 16-bit CMOS CPU is manufactured using a

hardened field, self aligned silicon gate CMOS process. Two

modes of operation, MINimum for small systems and

MAXimum for larger applications such as multiprocessing,

allow user configuration to achieve the highest performance

level. Industry standard operation allows use of existing

NMOS 8086 hardware and software designs.

Specifications for Rad Hard QML devices are controlled

by the Defense Supply Center in Columbus (DSCC). The

SMD numbers listed here must be used when ordering.

Detailed Electrical Specifications for these devices are

contained in SMD 5962-95722. A “hot-link” is provided

on our homepage for downloading.

www.intersil.com/spacedefense/space.asp

FN3035

Rev 0.00

August 2000

Features

• Electrically Screened to SMD # 5962-95722

• QML Qualified per MIL-PRF-38535 Requirements

• Radiation Performance

- Latch Up Free EPl-CMOS

- Total Dose. . . . . . . . . . . . . . . . . . . . . 100 krad(Si) (Max)

- Transient Upset . . . . . . . . . . . . . . . . . . . .>10

rad(Si)/s

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . .500A (Max)

- ICCOP . . . . . . . . . . . . . . . . . . . . . . . 12mA/MHz (Max)

• Pin Compatible with NMOS 8086 and Intersil 80C86

• Completely Static Design DC to 5MHz

• 1MB Direct Memory Addressing Capability

• 24 Operand Addressing Modes

Ordering Information

ORDERING NUMBER

5962R9572201QQC

5962R9572201QXC

5962R9572201VQC

5962R9572201VXC

HS1-80C86RH/Proto

HS9-80C86RH/Proto

INTERNAL

MKT. NUMBER

HS1-80C86RH-8

HS9-80C86RH-8

HS1-80C86RH-Q

HS9-80C86RH-Q

HS1-80C86RH/Proto

HS9-80C86RH/Proto

TEMP. RANGE

(

-55 to 125

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

- Binary or Decimal

- Multiply and Divide

• Bus-Hold Circuitry Eliminates Pull-up Resistors for CMOS

Designs

• Hardened Field, Self-Aligned, Junction-Isolated CMOS

Process

• Single 5V Power Supply

• Military Temperature Range . . . . . . . . . . . -35

C to 125

• Minimum LET for

Single Event Upset . . . . . . . . . . . . . 6MEV/mg/cm

(Typ)

FN3035 Rev 0.00

August 2000

Page 1 of 30

HS-80C86RH

Pin Descriptions

SYMBOL

NUMBER

TYPE

DESCRIPTION

The following pin function descriptions are for HS-80C86RH systems in either minimum or maximum mode. The “Local Bus” in these descriptions

is the direct multiplexed bus interface connection to the HS-80C86RH (without regard to additional bus buffers).

AD15-AD0

2-16, 39

I/O

ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data

(T2, T3, TW, T4) bus. AO is analogous to BHE for the lower byte of the data bus, pins D7-D0. It is LOW

during T1 when a byte is to be transferred on the lower portion of the bus in memory or I/O operations.

Eight-bit oriented devices tied to the lower half would normally use AD0 to condition chip select functions

(See BHE). These lines are active HIGH and are held at high impedance to the last valid logic level during

interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.

ADDRESS/STATUS: During T1, these are the four most significant address lines for memory operations.

During I/O operations these lines are low. During memory and I/O operations, status information is

available on these lines during T2, T3, TW, T4. S6 is always zero. The status of the interrupt enable FLAG

bit (S5) is updated at the beginning of each CLK cycle. S4 and S3 are encoded.

This information indicates which segment register is presently being used for data accessing. These lines

are held at high impedance to the last valid logic level during local bus “hold acknowledge” or “grant

sequence”.

BHE/S7

Extra Data

Stack

Code or None

Data

A19/S6

A18/S5

A17/S4

A16/S3

35-38

BUS HIGH ENABLE/STATUS: During T1 the bus high enable signal (BHE) should be used to enable

data onto the most significant half of the data bus, pins D15-D8. Eight bit oriented devices tied to the

upper half of the bus would normally use BHE to condition chip select functions. BHE is LOW during T1

for read, write, and interrupt acknowledge cycles when a byte is to be transferred on the high portion of

the bus. The S7 status information is available during T2, T3 and T4. The signal is active LOW, and is

held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold

acknowledge” or “grant sequence”; it is LOW during T1 for the first interrupt acknowledge cycle.

BHE

Whole Word

Upper Byte from/to Odd Address

Lower Byte from/to Even Address

None

READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending

on the state of the M/IO or S2 pin. This signal is used to read devices which reside on the HS-80C86RH

local bus. RD is active LOW during T2, T3 and TW of any read cycle, and is guaranteed to remain HIGH

in T2 until the 80C86 local bus has floated.

This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

READY

READY: is the acknowledgment from the addressed memory or I/O device that will complete the data

transfer. The RDY signal from memory or I/O is synchronized by the HS-82C85RH Clock Generator to

form READY. This signal is active HIGH. The HS-80C86RH READY input is not synchronized. Correct

operation is not guaranteed if the Setup and Hold Times are not met.

INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each

instruction to determine if the processor should enter into an interrupt acknowledge operation. If so, an

interrupt service routine is called via an interrupt vector lookup table located in system memory. INTR is

internally synchronized and can be internally masked by software resetting the interrupt enable bit. This

signal is active HIGH.

TEST: input is examined by the “Wait” instruction. If the TEST input is LOW execution continues,

otherwise the processor waits in an “Idle” state. This input is synchronized internally during each clock

cycle on the leading edge of CLK.

INTR

TEST

FN3035 Rev 0.00

August 2000

Page 4 of 30

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