8N4Q001LG-0155CDI datasheet, PDF

Datasheet> All Categories > Passive components> 8N4Q001LG-0155CDI

8N4Q001LG-0155CDI: DescriptionProgrammable Oscillators; CategoryPassive components; File Size163KB，20 Pages; ManufacturerIDT (Integrated Device Technology)

Download Datasheet Parametric View All

8N4Q001LG-0155CDI Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	8N4Q001LG-0155CDI	-	-	View	Buy Now

8N4Q001LG-0155CDI Overview

Programmable Oscillators

8N4Q001LG-0155CDI Parametric

Parameter Name	Attribute value
Product Attribute	Attribute Value
Manufacturer	IDT (Integrated Device Technology)
Product Category	Programmable Oscillators
Product	XO

Preview

Download Datasheet

View All

Quad-Frequency Programmable XO IDT8N4Q001 REV G

DATA SHEET

General Description

The IDT8N4Q001 is a Quad-Frequency Programmable Clock

Oscillator with very flexible frequency programming capabilities. The

device uses IDT’s fourth generation FemtoClock® NG technology for

an optimum high clock frequency and low phase noise performance.

The device accepts 2.5V or 3.3V supply and is packaged in a small,

lead-free (RoHS 6) 10-lead ceramic 5mm x 7mm x 1.55mm package.

Besides the four default power-up frequencies set by the FSEL0 and

FSEL1 pins, the IDT8N4Q001 can be programmed via the I

interface to output clock frequencies between 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz to a very high degree of

precision with a frequency step size of 435.9Hz ÷

(N is the PLL

output divider). Since the FSEL0 and FSEL1 pins are mapped to four

independent PLL divider registers (P, MINT, MFRAC and N),

reprogramming those registers to other frequencies under control of

FSEL0 and FSEL1 is supported. The extended temperature range

supports wireless infrastructure, telecommunication and networking

end equipment requirements.

Features

•

Fourth generation FemtoClock® NG technology

Programmable clock output frequency from 15.476MHz to

866.67MHz and from 975MHz to 1,300MHz

Four power-up default frequencies (see part number order

codes), re-programmable by I

C programming interface for the output clock frequency and

internal PLL control registers

Frequency programming resolution is 435.9Hz ÷N

One 2.5V, 3.3V LVDS clock output

Two control inputs for the power-up default frequency

LVCMOS/LVTTL compatible control inputs

RMS phase jitter @ 156.25MHz (12kHz - 20MHz): 0.253ps

(typical), integer PLL feedback configuration

RMS phase jitter @ 156.25MHz (1kHz - 40MHz): 0.263ps

(typical), integer PLL feedback configuration

Full 2.5V or 3.3V supply modes

-40°C to 85°C ambient operating temperature

Available in Lead-free (RoHS 6) package

Block Diagram

OSC

XTAL

÷MINT,

MFRAC

FSEL1

FSEL0

SCLK

SDATA

Pulldown

Pullup

Pin Assignment

÷P

PFD

LPF

FemtoClock® NG

VCO

1950-2600MHz

÷N

Q

DNU 1

OE 2

GND 3

FSEL0 4

FSEL1 5

10 SCLK

9 SDATA

8 V

7 nQ

6 Q

Configuration Register (ROM)

(Frequency, APR, Polarity)

C Control

IDT8N4Q001

10-lead ceramic 5mm x 7mm x 1.55mm

package body

CD Package

Top View

IDT8N4Q001GCD

REVISION A

MARCH 6, 2012

Recommended Resources

A high-fidelity pre- and post-amplifier 03

HT-2821 series (dual tone) circuit

Practical circuit diagram of main power supply and auxiliary power supply

IR sensor and monitor wake up the main system circuit

L292 extended output current circuit

Piao SIPMOS control circuit using transformer potential isolation

Is there something wrong with the disk? How to solve it? Waiting for a reply online, thank you...: The computer I am using now, Win2000 Pro system, occasionally restarts automatically. It is under normal operation, without any prompt, and the system automatically restarts! The system has just been ...; lingjian1026 Embedded System

About AGC circuit based on AD603: [i=s] This post was last edited by paulhyde on 2014-9-15 03:09 [/i] Because the 9854 has a strong attenuation in the high frequency area, I want to use AGC, but the typical AGC circuit of AD603 cannot...; kcookey Electronics Design Contest

[CN0175] Low-Cost, 8-Channel, Simultaneous Sampling Data Acquisition System with 84 dB SNR and Channel-to-Channel Matching: Circuit Function and BenefitsFor low cost, high channel count applications requiring wide dynamic range, the AD7607 8-channel integrated data acquisition system (DAS) with an on-chip 14-bit SAR ADC ca...; EEWORLD社区 ADI Reference Circuit

Help!! There is a problem with the waveform time-delay copy.: I would like to ask a tricky question. The code is to divide the CP input signal and output PCI1_CLK and PCI2_CLK. The interval time of the divided signal is that PCI2_CLK is a delayed copy of PCI1_CL...; yekeyaopei FPGA/CPLD

555 circuit (Protel simulation) video tutorial: [flash]http://player.youku.com/player.php/sid/XMjA3ODM0ODAw/v.swf[/flash]Share with you...; lilong8470 Analog electronics

Comprehensive error problem: I encountered the following problem when doing a design: there was no problem in the previous simulation, but the following error occurred during synthesis: cannot mix blocking and non blocking assign...; zhgshi FPGA/CPLD

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components