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9DB102BGILFT

Description
TSSOP-20, Reel
Categorylogic   
File Size266KB,14 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
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9DB102BGILFT Overview

TSSOP-20, Reel

9DB102BGILFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTSSOP
package instructionTSSOP-20
Contacts20
Manufacturer packaging codePGG20
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys Confidence3
Samacsys StatusReleased
Samacsys PartID1460492
Samacsys Pin Count20
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategorySmall Outline Packages
Samacsys Footprint NamePCG20
Samacsys Released Date2020-01-17 14:50:44
Is SamacsysN
series9DB
Input adjustmentDIFFERENTIAL
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length6.5 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals20
Actual output times2
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP20,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Prop。Delay @ Nom-Sup0.15 ns
propagation delay (tpd)0.15 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.025 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width4.4 mm
Base Number Matches1
DATASHEET
Two Output Differential Buffer for PCIe Gen1 & Gen2
Description
The
ICS9DB102
zero-delay buffer supports PCI Express
clocking requirements. The
ICS9DB102
is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
ICS9DB102
Features/Benefits
CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
PLL or bypass mode/PLL can dejitter incoming clock
Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
Spread Spectrum Compatible/tracks spreading input clock
for low EMI
SMBus Interface/unused outputs can be disabled
Industrial temperature range available
Output Features
2 - 0.7V current mode differential output pairs (HCSL)
Key Specifications
Cycle-to-cycle jitter < 35ps
Output-to-output skew < 25ps
Functional Block Diagram
CLKREQ0#
CLKREQ1#
PCIEX0
CLK_INT
SPREAD
COMPATIBLE
PLL
PCIEX1
C LK_IN C
PLL_BW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV Q 08/27/13
1

9DB102BGILFT Related Products

9DB102BGILFT 9DB102BGLFT 9DB102BGLF 9DB102BFLF
Description TSSOP-20, Reel TSSOP-20, Reel TSSOP-20, Tube QSOP-20, Tube
Brand Name Integrated Device Technology Integrated Device Technology Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free Lead free Lead free
Is it Rohs certified? conform to conform to conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TSSOP TSSOP TSSOP QSOP
package instruction TSSOP-20 TSSOP-20 TSSOP-20 SSOP-20
Contacts 20 20 20 20
Manufacturer packaging code PGG20 PGG20 PGG20 PCG20
Reach Compliance Code compliant compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99
series 9DB 9DB 9DB 9DB
Input adjustment DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL DIFFERENTIAL
JESD-30 code R-PDSO-G20 R-PDSO-G20 R-PDSO-G20 R-PDSO-G20
JESD-609 code e3 e3 e3 e3
length 6.5 mm 6.5 mm 6.5 mm 8.65 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Humidity sensitivity level 1 1 1 1
Number of functions 1 1 1 1
Number of terminals 20 20 20 20
Actual output times 2 2 2 2
Maximum operating temperature 85 °C 70 °C 70 °C 70 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code TSSOP TSSOP TSSOP SSOP
Encapsulate equivalent code TSSOP20,.25 TSSOP20,.25 TSSOP20,.25 SSOP20,.25
Package shape RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
Peak Reflow Temperature (Celsius) 260 260 260 260
power supply 3.3 V 3.3 V 3.3 V 3.3 V
Prop。Delay @ Nom-Sup 0.15 ns 0.185 ns 0.185 ns 0.185 ns
propagation delay (tpd) 0.15 ns 0.15 ns 0.15 ns 0.15 ns
Certification status Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.025 ns 0.025 ns 0.025 ns 0.025 ns
Maximum seat height 1.2 mm 1.2 mm 1.2 mm 1.75 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES
Temperature level INDUSTRIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm 0.65 mm 0.635 mm
Terminal location DUAL DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
width 4.4 mm 4.4 mm 4.4 mm 3.9 mm
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