Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
1
through I/O
8
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
9
through I/O
16
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
1
to I/O
8
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
9
to I/O
16.
See the
truth table at the back of this data sheet for a complete descrip-
tion of read and write modes.
The input/output pins (I/O
1
through I/O
16
) are placed in a
high-impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and
BLE are disabled (BHE, BLE HIGH), or during a write opera-
tion (CE LOW, and WE LOW).
The CY7C1021BV is available in 400-mil-wide SOJ, standard
44-pin TSOP Type II, and 48-ball mini BGA packages.
Functional Description
[1]
The CY7C1021BV is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an au-
tomatic power-down feature that significantly reduces power
consumption when deselected.
Logic Block Diagram
DATA IN DRIVERS
Pin Configurations
SOJ / TSOP II
Top View
A
4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
V
CC
V
SS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
64K x 16
RAM Array
512 X 2048
I/O
1
–I/O
8
I/O
9
–I/O
16
COLUMN DECODER
BHE
WE
CE
OE
BLE
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
V
SS
V
CC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
ROW DECODER
Selection Guide
7C1021BV-8
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current
(mA)
Commercial
Industrial
Commercial
L
8
170
190
5
0.500
7C1021BV-10
10
160
180
5
0.500
7C1021BV-12
12
150
170
5
0.500
7C1021BV-15
15
140
160
5
0.500
Shaded areas contain advance information.
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05148 Rev. *A
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
•
SENSE AMPS
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 13, 2002
CY7C1021BV33
Pin Configurations
Mini BGA
(Top View)
1
BLE
2
OE
3
A
0
4
A
1
5
A
2
CE
I/O
2
6
NC
I/O
1
I/O
3
A
B
C
D
E
F
G
H
I/O
9
BHE
I/O
10
I/O
11
A
3
A
5
A
4
A
6
A
7
NC
V
SS
I/O
12
NC
V
CC
I/O
13
NC
I/O
15
I/O
14
A
14
I/O
16
NC
NC
A
8
A
12
A
9
I/O
4
V
CC
I/O
5
V
SS
I/O
7
A
15
I/O
6
A
13
A
10
WE I/O
8
A
11
NC
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[2]
.... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High Z State
[2]
......................................–0.5V to V
CC
+0.5V
DC Input Voltage
[2]
...................................–0.5V
Current into Outputs (LOW) ........................................ 20 mA
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V
±
10%
3.3V
±
10%
to V
CC
+0.5V
Note:
2. Mimimum voltage is–2.0V for pulse durations of less than 20 ns.
Document #: 38-05148 Rev. *A
Page 2 of 11
CY7C1021BV33
Electrical Characteristics
Over the Operating Range
7C1021BV-8
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH
Voltage
Input LOW
Voltage
[2]
Input Load
Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-Down
Current
—TTL Inputs
Automatic CE
Power-Down
Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
I
< V
CC
,
Output Disabled
V
CC
= Max.,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
,
CE > V
IH
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V, L
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V,
f=0
Com
Ind
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
2.2
−0.3
−1
−1
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+1
170
190
40
2.2
−0.3
−1
−1
Max.
7C1021BV-10
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+1
160
120
40
2.2
–0.3
–1
–1
Max.
7C1021BV-12
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+1
150
170
40
2.2
–0.3
–1
–1
Max.
7C1021BV-15
Min.
2.4
0.4
V
CC
+
0.3V
0.8
+1
+1
140
160
40
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
I
SB1
I
SB2
5
500
5
500
5
500
5
500
mA
µA
Shaded areas contain advance information.
Capacitance
[3]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
Max.
6
8
Unit
pF
pF
Note:
3. Tested initially and after any design or process changes that may affect these parameters.
AC Test Loads and Waveforms
3.3V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
R2
351Ω
R 317Ω
R 317Ω
3.3V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
R2
351Ω
GND
Rise Time: 1 V/ns
3.0V
10%
ALL INPUT PULSES
90%
90%
10%
(b)
Fall Time: 1 V/ns
167
OUTPUT
Equivalent to: THÉVENIN
EQUIVALENT
30 pF
1.73V
Document #: 38-05148 Rev. *A
Page 3 of 11
CY7C1021BV33
Switching Characteristics
[4]
Over the Operating Range
7C1021BV-8
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
[5, 6]
CE LOW to Low Z
[6]
CE HIGH to High Z
[5, 6]
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
CYCLE
[7]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[5, 6]
Byte Enable to End of Write
8
8
7
6
0
0
6
4
0
3
4
8
10
8
7
0
0
8
6
0
3
5
8
12
9
8
0
0
8
6
0
3
6
9
15
10
10
0
0
10
8
0
3
7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
0
4
0
5
0
12
3
4
0
12
5
0
6
0
4
3
5
0
12
6
0
7
3
8
4
0
5
3
6
0
15
7
8
8
3
10
4
0
6
3
7
10
10
3
12
6
0
7
12
12
3
15
7
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C1021BV-10
Min.
Max.
7C1021BV-12
Min.
Max.
7C1021BV-15
Min.
Max.
Unit
Shaded areas contain advance information.
Data Retention Characteristics
Over the Operating Range (L version only)
Parameter
V
DR
I
CCDR
t
CDR[9]
t
R[10]
Description
V
CC
for Data Retention
Data Retention Current
Com’l
V
CC
= V
DR
= 2.0V,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V or V
IN
< 0.3V
0
t
RC
Conditions
[8]
Min.
2.0
100
Max.
Unit
V
µA
Chip Deselect to Data Retention Time
Operation Recovery Time
ns
ns
Notes:
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
5. t
HZOE
, t
HZBE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured
±500
mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE / BLE LOW. CE, WE and BHE / BLE must be LOW to initiate a write,
and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. No input may exceed V
CC
+ 0.5V.
9. Tested initially and after any design or process changes that may affect these parameters.
10. t
r
< 3 ns for the -12 and -15 speeds. t
r
< 5 ns for the -20 and slower speeds.
Document #: 38-05148 Rev. *A
Page 4 of 11
CY7C1021BV33
Data Retention Waveform
DATA RETENTION MODE
V
CC
3.0V
t
CDR
CE
V
DR
>
2V
3.0V
t
R
Switching Waveforms
Read Cycle No. 1
[11, 12]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)
ADDRESS
[12, 13]
t
RC
CE
t
ACE
OE
BHE, BLE
t
DOE
t
LZOE
t
DBE
t
LZBE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
HZCE
t
HZBE
DATA VALID
t
PD
50%
IISB
SB
IICC
CC
t
HZOE
HIGH
IMPEDANCE
DATA OUT
Notes:
11. Device is continuously selected. OE, CE, BHE and/or BHE = V
IL
.
12. WE is HIGH for read cycle.
13. Address valid prior to or coincident with CE transition LOW.
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