INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
•
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT4020
14-stage binary ripple counter
Product specification
File under Integrated Circuits, IC06
September 1993
Philips Semiconductors
Product specification
14-stage binary ripple counter
FEATURES
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT4020 are high-speed Si-gate CMOS
devices and are pin compatible with the “4020” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT4020
The 74HC/HCT4020 are 14-stage binary ripple counters
with a clock input (CP), an overriding asynchronous
master reset input (MR) and twelve fully buffered parallel
outputs (Q
0
, Q
3
to Q
13
).
The counter is advanced on the HIGH-to-LOW transition of
CP.
A HIGH on MR clears all counter stages and forces all
outputs LOW, independent of the state of CP.
Each counter stage is a static toggle flip-flop.
TYPICAL
SYMBOL
t
PHL/
t
PLH
PARAMETER
propagation delay
CP to Q
0
Q
n
to Q
n+1
MR to Q
n
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
11
6
17
101
3.5
19
15
6
19
52
3.5
20
ns
ns
ns
MHz
pF
pF
HCT
UNIT
September 1993
2
Philips Semiconductors
Product specification
14-stage binary ripple counter
PIN DESCRIPTION
PIN NO.
8
10
11
16
SYMBOL
parallel outputs
ground (0 V)
GND
CP
MR
V
CC
74HC/HCT4020
NAME AND FUNCTION
9, 7, 5, 4, 6, 13, 12, 14, 15, 1, 2, 3 Q
0
, Q
3
to Q
13
clock input (HIGH-to-LOW, edge-triggered)
master reset input (active HIGH)
positive supply voltage
fpage
RCTR14
0
3
CT=0
CT
13
MGA829
9
7
5
4
6
13
12
14
15
1
2
3
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
September 1993
3
Philips Semiconductors
Product specification
14-stage binary ripple counter
74HC/HCT4020
FUNCTION TABLE
INPUTS
CP
↑
↓
X
Notes
MR
L
L
H
OUTPUTS
Q
0
, Q
3
to Q
13
no change
count
L
Fig.4 Functional diagram.
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑
= LOW-to-HIGH clock
transition
↓
= HIGH-to-LOW clock
transition
Fig.5 Logic diagram.
Fig.6 Timing diagram.
September 1993
4
Philips Semiconductors
Product specification
14-stage binary ripple counter
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
74HC
SYMBOL
PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
CP to Q
0
propagation delay
Q
n
to Q
n+1
propagation delay
MR to Q
n
output transition time
+25
typ.
39
14
11
22
8
6
55
20
16
19
7
6
80
16
14
11
4
3
17
6
5
6
2
2
30
92
109
max.
140
28
24
75
15
13
170
34
29
75
15
13
100
20
17
100
20
17
65
13
11
4.8
24
28
−40
to
+85
min.
max.
175
35
30
95
19
16
215
43
37
95
19
16
120
24
20
120
24
20
75
15
13
4.0
20
24
−40
to
+125
min.
max.
210
42
36
110
22
19
225
51
43
110
22
19
74HC/HCT4020
TEST CONDITIONS
UNIT V
WAVEFORMS
CC
(V)
ns
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
ns
Fig.7
t
PHL
ns
Fig.8
t
THL
/ t
TLH
ns
Fig.7
t
W
clock pulse width
HIGH or LOW
ns
Fig.7
t
W
master reset pulse width 80
HIGH
16
14
removal time
MR to CP
maximum clock pulse
frequency
50
10
9
6.0
30
35
ns
Fig.8
t
rem
ns
Fig.8
f
max
MHz
Fig.7
September 1993
5
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