HI-8570, HI-8571
August 2006
+/- 5V Supply, ARINC 429 LINE DRIVER
PIN CONFIGURATION
SLP1.5
1
TX0IN
2
TX1IN
3
GND
4
DESCRIPTION
The HI-8570 and HI-8571 are CMOS integrated circuits
designed to directly drive the ARINC 429 bus in an 8-pin
package. Two logic inputs control a differential voltage
between the output pins producing a +10 volt One, a
-10 volt Zero, and a 0 volt Null.
A logic input is provided to control the slope of the
differential output signal. Timing is set by an on-chip
resistor and capacitor and tested to be within ARINC
requirements.
The HI-8570 has 37.5 ohms in series with each line driver
output. The HI-8571 provides the option to bypass part of
the output resistance so external resistance may be
added for lightning protection circuits.
The HI-8570 or the HI-8571 along with the HI-8588 line
receiver offer the smallest options available to get on and
off theARINC 429 bus.
8
V+
7
TXBOUT
6
TXAOUT
5
V-
SUPPLY VOLTAGES
V+ = +5V
V- = -5V
FUNCTION TABLE
TX1IN TX0IN SLP1.5
TXAOUT
0V
-5V
-5V
5V
5V
0V
TXBOUT
0V
5V
5V
-5V
-5V
0V
SLOPE
N/A
10
m
s
1.5
m
s
10
m
s
1.5
m
s
N/A
0
0
0
0
1
1
0
0
1
X
0
1
0
1
X
FEATURES
!
!
!
!
!
!
!
Direct ARINC 429 line driver interface
in a small package
On-chip line driver slope control and
selection by logic input
Low current 5 volt supplies
CMOS / TTL logic pins
1
1
1
PIN DESCRIPTION TABLE
PIN
SYMBOL
SLP 1.5
TX0IN
TX1IN
GND
V-
TXAOUT
TXBOUT
V+
FUNCTION
LOGIC INPUT
LOGIC INPUT
LOGIC INPUT
POWER
POWER
OUTPUT
OUTPUT
POWER
DESCRIPTION
CMOS OR TTL, V+ IS OK
CMOS OR TTL
CMOS OR TTL
GROUND
-5 VOLTS
LINE DRIVER TERMINAL A
LINE DRIVER TERMINAL B
+5 VOLTS
1
2
3
Plastic and ceramic package options -
surface mount and DIP
Thermally enhanced SOIC packages
Mil processing available
4
5
6
7
8
(DS8570 Rev. B)
HOLT INTEGRATED CIRCUITS
www.holtic.com
08/06
HI-8570, HI-8571
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the line driver. The +5V and
-5V levels are generated from the supply voltages. Cur-
rents for slope control are set by zener voltages across on-
chip resistors.
The TX0IN and TX1IN inputs receive logic signals from a
control transmitter chip such as the HI-6010, HI-3282, HI-
8282A, HI-8584 or HI-8783. TXAOUT and TXBOUT hold
each side of the ARINC bus at Ground until one of the
inputs becomes a One. If for example TX1IN goes high, a
charging path is enabled to 5V on an “A” side internal
capacitor while the “B” side is enabled to -5V. The charg-
ing current is selected by the SLP1.5 pin. If the SLP1.5
pin is high, the capacitor is nominally charged from 10% to
90% in 1.5µs. If SLP1.5 is low, the rise and fall times are
10µs.
A unity gain buffer receives the internally generated slopes
and differentially drives the ARINC line. Current is limited
by the series output resistors at each pin. There are no
fuses at the outputs of the HI-8570 as exists on the HI-
8382.
The HI-8570 has 37.5 ohms in series with each output and
the HI-8571 has 27.5 ohms in series with each output.
The HI-8571 is for applications where external series re-
sistance is required, typically for lightning protection de-
vices.
Both the HI-8570 and HI-8571 are built using high-speed
CMOS technology. Care should be taken to ensure the
V+ and V- supplies are locally decoupled and that the
input waveforms are free from negative voltage spikes
which may upset the chip’s internal slope control circuitry.
5V
ONE
“A” SIDE
CURRENT
CONTROL
TXAOUT
HI-8570 = 37.5 OHMS
HI-8571 = 27.5 OHMS
NULL
ZERO
-5V
TX0IN
TX1IN
ESD
PROTECTION
AND
VOLTAGE
TRANSLATION
CONTROL
LOGIC
SLP1.5
5V
ONE
“B” SIDE
CURRENT
CONTROL
TXBOUT
HI-8570 = 37.5 OHMS
HI-8571 = 27.5 OHMS
NULL
ZERO
CONTROL
LOGIC
-5V
FIGURE 1 - LINE DRIVER BLOCK DIAGRAM
5V
1
HARDWIRED
OR
DRIVEN FROM LOGIC
{
2
8
4
VCC
TESTA
TESTB
ROUTA
ROUTB
6
7
RXD1
RXD0
HI-8588
RINA
RINB
APPLICATION INFORMATION
Figure 2 shows a possible application
of the HI-8570/8571 interfacing an
ARINC transmit channel from the HI-
6010.
ARINC
Channel
3
HI-6010
5
5V
1
6
SLP1.5
TXAOUT
8 BIT BUS
8
V+
TX1IN
TX0IN
V-
3
2
ARINC
Channel
TXD1
TXD0
7
HI-8570
TXBOUT
GND
4
5
-5V
FIGURE 2 - APPLICATION DIAGRAM
HOLT INTEGRATED CIRCUITS
2
HI-8570, HI-8571
ABSOLUTE MAXIMUM RATINGS
Voltages referenced to Ground
Supply voltages
V+....................................................+7V
V-......................................................-7V
DC current per input pin................. +10mA
Power dissipation at 25°C
plastic DIL............1.0W, derate 10mW/°C
ceramic DIL..........0.5W, derate 7mW/°C
Solder Temperature ........275°C for 10 sec
Storage Temperature........-65°C to +150°C
NOTE: Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to
the device. These are stress ratings only.
Operation at the limits is not recommended.
RECOMMENDED OPERATING CONDITIONS
Supply Voltages
V+....................................+4.8V to +5.3V
V-..................................... -5.3V to -4.8V
Temperature Range
Industrial Screening.........-40°C to +85°C
Hi-Temp Screening........-55°C to +125°C
Military Screening..........-55°C to +125°C
DC ELECTRICAL CHARACTERISTICS
V+ = +5V, V- = -5V, T
A
= Operating Temperature Range (unless otherwise stated)
PARAMETERS
Input voltage (TX1IN, TX0IN, SLP1.5)
high
low
Input current (TX1IN, TX0IN, SLP1.5)
source
sink
ARINC output voltage (Differential)
one
zero
null
ARINC output voltage (Ref. to GND)
one or zero
null
Operating supply current
V+
V-
ARINC output impedence
HI-8570
HI-8571
SYMBOL
V
IH
V
IL
TEST CONDITIONS
MIN
2.1
-
TYP
-
-
MAX
V+
0.5
UNITS
volts
volts
I
IH
I
IL
V
IN
= 0V
V
IN
= 5V
-
-
-
-
0.1
0.1
m
A
m
A
V
DIFF1
V
DIFF0
V
DIFFN
no load; TXAOUT - TXBOUT
9.00
no load; TXAOUT - TXBOUT -11.00
no load; TXAOUT - TXBOUT -0.50
10.00
-10.00
0
11.00
-9.00
0.50
volts
volts
volts
V
DOUT
V
NOUT
no load & magnitude at pin
no load
SLP1.5 = V+
TX1IN & TX0IN = 0V: no load
TX0IN & TX1IN = 0V: no load
4.50
-0.25
5.00
0
5.50
0.25
volts
volts
I
DD
I
EE
Z
OUT
-
-10.0
6.0
-6.0
10.0
-
mA
mA
-
-
37.5
27.5
-
-
ohms
ohms
HOLT INTEGRATED CIRCUITS
3
HI-8570, HI-8571
AC ELECTRICAL CHARACTERISTICS
V+ = 5.0V, V- = -5V, T
A
= Operating Temperature Range (unless otherwise stated)
PARAMETERS
Line Driver propagation delay
Output high to low
Output low to high
Line Driver transition times
High Speed
Output high to low
Output low to high
Low Speed
Output high to low
Output low to high
Input capacitance (1)
logic
Notes:
1. Guaranteed but not tested
t phlx
t plhx
SLP 1.5 = V+
pin 1 = logic 1
pin 1 = logic 1
SLP 1.5 = GND
pin 1 = logic 1
pin 1 = logic 1
SYMBOL
TEST CONDITIONS
defined in Figure 3, no load
-
-
500
500
-
-
ns
ns
MIN
TYP
MAX
UNITS
t fx
t rx
t fx
t rx
1.0
1.0
5.0
5.0
1.5
1.5
10.0
10.0
2.0
2.0
15.0
15.0
µs
µs
µs
µs
CIN
-
-
10
pF
pin 3
t phlx
t plhx
pin 2
t phlx
t rx
t rx
VDIFF
pin 6 - pin 7
90%
10%
90%
10%
10%
5V
0V
t plhx
5V
0V
10V
0V
-10V
t fx
t fx
FIGURE 3 - LINE DRIVER TIMING
HOLT INTEGRATED CIRCUITS
4
HI-8570, HI-8571
PACKAGE THERMAL CHARACTERISTICS
Maximum ARINC Load
PACKAGE STYLE
1
ARINC 429
DATA RATE
Low Speed
3
High Speed
4
SUPPLY CURRENT (mA)
Ta = 25
°
C
Ta = 85
°
C
2
JUNCTION TEMP, Tj
°
C
Ta = 25
°
C
Ta = 85
°
C
Ta = 125
°
C
Ta = 125
°
C
8 Lead Plastic ESOIC
5
20.98
26.40
20.96
26.16
20.96
25.96
38.24
44.78
98.34
104.66
138.92
144.59
TXAOUT and TXBOUT Shorted to Ground
PACKAGE STYLE
1
6,7,8
ARINC 429
DATA RATE
Low Speed
3
SUPPLY CURRENT (mA)
Ta = 25
°
C
Ta = 85
°
C
2
JUNCTION TEMP, Tj
°
C
Ta = 25
°
C
Ta = 85
°
C
Ta = 125
°
C
Ta = 125
°
C
8 Lead Plastic ESOIC
5
30.26
30.44
29.22
29.42
28.46
28.68
53.75
53.92
112.76
112.95
152.04
152.25
High Speed
4
Notes:
1. All data taken in still air.
2. At 100% duty cycle, 5V power supplies.
3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF.
4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF
as this is considered unrealistic for high speed operation.
5. 8 Lead Plastic ESOIC (Thermally enhanced SOIC with built in heat sink). Heat sink not soldered.
6. Similar results would be obtained with TXAOUT shorted to TXBOUT.
7. For applications requiring survival with continuous short circuit, operation above Tj = 175°C is not recommended.
8. Data will vary depending on air flow and the method of heat sinking employed.
HEAT SINK - ESOIC PACKAGES
An 8-pin thermally enhanced SOIC package is used for the
HI-8570/HI-8571 products. The ESOIC package includes
a metal heat sink located on the bottom surface of the
device. This heat sink should be soldered down to the
printed circuit board for optimum thermal dissipation. The
heat sink is electrically isolated from the chip and can be
soldered to any ground or power plane. However, since
the chip’s substrate is at V+, connecting the heat sink to
this power plane is recommended to avoid coupling noise
into the circuit.
HOLT INTEGRATED CIRCUITS
5
京公网安备 11010802033920号
EEWORLD
