PCK351
1:10 clock distribution device with 3-State outputs
Rev. 01 — 14 May 2002
Product data
1. Description
The PCK351 is a high-performance 3.3 V LVTTL clock distribution device. The
PCK351 enables a single clock input to be distributed to ten outputs with minimum
output skew and pulse skew. The use of distributed V
CC
and GND pins in the PCK351
ensures reduced switching noise.
The PCK351 is characterized for operation over the supply range 3.0 V to 3.6 V, and
over the industrial temperature range
−40
to +85
°C.
2. Features
s
s
s
s
s
s
s
s
s
s
1:10 LVTTL clock distribution
Low output to output skew
Low output pulse skew
Over voltage tolerant inputs and outputs
LVTTL-compatible inputs and outputs
Distributed V
CC
and ground pins reduce switching noise
Balanced High-drive outputs (−32 mA I
OH
, 32 mA I
OL
)
Reduced power dissipation due to the state-of-the-art QUBiC-LP process
Supply range of +3.0 V to +3.6 V
Package options include plastic small-outline (D) and shrink small-outline (DB)
packages
s
Industrial temperature range
−40
to +85
°C
s
PCK351 is identical to and replaces PTN3151.
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Symbol
t
PHL
/t
PLH
C
I
C
O
C
PD
[1]
Parameter
propagation delay: A to Y
n
input capacitance
output capacitance
power dissipation capacitance
[1]
Conditions
C
L
= 50 pF; V
CC
= 3.3 V
V
I
= V
CC
or GND
V
I
= V
CC
or GND
C
L
= 50 pF; f = 1 MHz
Min
3.1
-
-
-
Typ
3.6
4
6
48
Max
4.1
-
-
-
Unit
ns
pF
pF
pF
C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
4. Ordering information
Table 2:
Ordering information
Package
Name
PCK351D
PCK351DB
SO24
SSOP24
Description
plastic small outline package; 24 leads; body width 7.5 mm
plastic shrink small outline package; 24 leads; body width 5.3 mm
Version
SOT137-1
SOT340-1
Type number
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
2 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
5. Pinning information
5.1 Pinning
GND
Y10
VCC
Y9
OE
A
GND
GND
Y8
1
2
3
4
5
24 GND
23 Y1
22 VCC
21 Y2
20 GND
GND 1
Y10 2
VCC 3
Y9 4
OE 5
24 GND
23 Y1
22 VCC
21 Y2
20 GND
6
7
8
9
19 Y3
18 Y4
17 GND
16 Y5
15 VCC
14 Y6
13 GND
PCK351DB
PCK351D
A 6
GND 7
GND 8
Y8 9
VCC 10
Y7 11
GND 12
19 Y3
18 Y4
17 GND
16 Y5
15 VCC
14 Y6
13 GND
VCC 10
Y7 11
GND 12
002aaa280
002aaa281
Fig 1. SO24 pin configuration.
Fig 2. SSOP24 pin configuration.
5.2 Pin description
Table 3:
Symbol
GND
Y
10
to Y
1
V
CC
OE
A
Pin description
Pin
1, 7, 8, 12, 13, 17, 20, 24
2, 4, 9, 11, 14, 16, 18, 19, 21, 23
3, 10, 15, 22
5
6
Description
ground (0 V)
outputs
supply voltage
output enable input (Active-LOW)
data input
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
3 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
6. Functional description
6.1 Function table
Table 4:
Function table
Inputs
A
L
H
L
H
[1]
H = HIGH voltage level;
L = LOW voltage level;
Z = high-impedance OFF-state.
Outputs
OE
H
H
L
L
Y
n
Z
Z
L
H
6.2 Logic symbol
OE
5
EN
23
21
19
18
A
6
16
14
11
9
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
4
Y9
2
Y10
002aaa283
Fig 3. Logic symbol.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
4 of 17
Philips Semiconductors
PCK351
1:10 clock distribution device with 3-State outputs
6.3 Logic diagram
5
OE
23
Y1
21
Y2
19
Y3
18
A
6
16
Y4
Y5
14
Y6
11
Y7
9
Y8
4
Y9
2
Y10
002aaa282
Fig 4. Logic diagram.
9397 750 09791
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Product data
Rev. 01 — 14 May 2002
5 of 17
京公网安备 11010802033920号
EEWORLD
