INTEGRATED CIRCUITS
DATA SHEET
SAA7158
Back END IC
Preliminary specification
File under Integrated Circuits, IC02
July 1994
Philips Semiconductors
Preliminary specification
Back END IC
FEATURES
•
Line Flicker Reduction (LFR) by means of MEDIAN filtering
•
Vertical zoom
•
Digital colour transient improvement
•
Digital luminance peaking
•
Movie phase detection
•
4:4:4 YUV data throughput selectable, standard is 4:1:1 Y/U/V
•
D/A conversion
•
UART interface.
GENERAL DESCRIPTION
Application Environment
SAA7158
The Back END IC (abbreviated as BENDIC) is designed to cooperate with an 8051 type of microprocessor, the ECO3
(SAA4951) memory controller and Texas Instruments TMS4C2970 memories, but other configurations may be
applicable. Fig.1 shows the block diagram of the feature box. The nominal clock frequency of the IC is 27 MHz or 32 MHz,
with a maximum of 36 MHz.
The system supports the digital Y/U/V bus for selection of different video signal sources. The Y/U/V bus and the BENDIC
data input are fully synchronous with respect to the clock signal. A line reference signal BLN for timing control purposes
has to be provided by external elements which always controls the system timing, independent of active signal sources
or desired functions.
Analog Characteristics
The BENDIC contains 3 independent, high speed digital to analog converters for luminance and colour difference signal
processing and conversion. The resolution of the two DA converters for the colour difference signals is 8 bit. The
luminance peaking up to 6 dB at high frequencies widens the resolution of the luminance channel. To avoid aliasing
effects due to time discrete amplitude limiting the resolution of 9-bit is offered for the luminance conversion. All output
stages provide high performance output stages for driving lines with low impedance line termination.
QUICK REFERENCE DATA
SYMBOL
V
DD
T
amb
digital supply voltage
analog supply voltage
operating ambient temperature
PARAMETER
MIN.
4.5
4.75
0
MAX.
5.5
5.25
+70
UNIT
V
V
°C
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
SAA7158WP
Note
1. SOT188-2; 1996 November 26.
PACKAGE
PINS
68
PIN POSITION
PLCC
MATERIAL
plastic
CODE
SOT188
(1)
July 1994
2
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
July 1994
3
Fig.1 Block diagram of the feature box.
Philips Semiconductors
Preliminary specification
Back END IC
PINNING
SYMBOL
TEST1/AP
Y0-0
Y0-1
Y0-2
Y0-3
Y0-4
Y0-5
V
DD1
V
SS1
Y0-6
Y0-7
UV0-0
UV0-1
UV0-2
UV0-3
TEST2/SP
RE2_OUT
RE1_OUT
RSTR
RE2_IN
RE1_IN
BLN
µPCL
µPDA
V
SS2
CLK
V
DD2
V1-0/Y2-0
V1-1/Y2-1
V1-2/Y2-2
V1-3/Y2-3
V1-4/Y2-4
V1-5/Y2-5
V1-6/Y2-6
V1-7/Y2-7
U1-0/UV2-0
U1-1/UV2-1
U1-2/UV2-2
U1-3/UV2-3
V
SS3
July 1994
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
input
3-state output
3-state output
3-state output
3-state output
3-state output
3-state output
supply
ground
3-state output
3-state output
3-state output
3-state output
3-state output
3-state output
input
output
output
input
input
input
input
input
in/output
ground
input
supply
input
input
input
input
input
input
input
input
input
input
input
input
ground
TYPE
DESCRIPTION
action pin for testing; to be connected to V
SS
feedback_data to second memory, Y bit 0
feedback_data to second memory, Y bit 1
feedback_data to second memory, Y bit 2
feedback_data to second memory, Y bit 3
feedback_data to second memory, Y bit 4
feedback_data to second memory, Y bit 5
positive digital supply voltage (+5 V)
digital ground
feedback_data to second memory, Y bit 6
feedback_data to second memory, Y bit 7
feedback_data to second memory, UV bit 0
feedback_data to second memory, UV bit 1
feedback_data to second memory, UV bit 2
feedback_data to second memory, UV bit 3
shift pin for testing; to be connected to V
SS
redirected read enable to memory 2
redirected read enable to memory 1
SAA7158
memory read,
µP
interface and movie detection reset
input for read enable to memory 2
input for read enable to memory 1
blanking signal
clock for interface with 8051 UART, mode 0
data for interface with 8051 UART, mode 0
digital ground
master clock, nominal 27 (32) MHz
positive digital supply voltage (+5 V)
V data, bit 0 in 4:4:4; Y data second memory, bit 0
V data, bit 1 in 4:4:4; Y data second memory, bit 1
V data, bit 2 in 4:4:4; Y data second memory, bit 2
V data, bit 3 in 4:4:4; Y data second memory, bit 3
V data, bit 4 in 4:4:4; Y data second memory, bit 4
V data, bit 5 in 4:4:4; Y data second memory, bit 5
V data, bit 6 in 4:4:4; Y data second memory, bit 6
V data, bit 7 in 4:4:4; Y data second memory, bit 7
U data, bit 0 in 4:4:4; UV data second memory, bit 0
U data, bit 1 in 4:4:4; UV data second memory, bit 1
U data, bit 2 in 4:4:4; UV data second memory, bit 2
U data, bit 3 in 4:4:4; UV data second memory, bit 3
digital ground
4
Philips Semiconductors
Preliminary specification
Back END IC
SAA7158
SYMBOL
U1-4/UV1-0
U1-5/UV1-1
U1-6/UV1-2
U1-7/UV1-3
Y1-0
Y1-1
Y1-2
Y1-3
Y1-4
Y1-5
Y1-6
Y1-7
V
SUB
RFHY
RFLY
RFLC
RFHC
V
DDA4
CUR
V
DDA3
AY
V
SSA3
V
DDA2
AU
V
SSA2
V
SSA1
AV
V
DDA1
PIN
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
input
input
input
input
input
input
input
input
input
input
input
input
TYPE
DESCRIPTION
U data, bit 4 in 4:4:4; UV data first memory, bit 0
U data, bit 5 in 4:4:4; UV data first memory, bit 1
U data, bit 6 in 4:4:4; UV data first memory, bit 2
U data, bit 7 in 4:4:4; UV data first memory, bit 3
Y data first memory, bit 0
Y data first memory, bit 1
Y data first memory, bit 2
Y data first memory, bit 3
Y data first memory, bit 4
Y data first memory, bit 5
Y data first memory, bit 6
Y data first memory, bit 7
substrate pin; connect to analog ground (V
SSA
)
connect C = 100 nF to analog ground (V
SSA
)
connect to analog ground (V
SSA
)
connect to analog ground (V
SSA
)
connect C = 100 nF to analog ground (V
SSA
)
analog supply voltage for reference ladders of the three DA
converters and for current sources of the output buffers
current input for analog output buffers (0.4 mA from V
DDA4
= 5 V);
connect with R = 15 kΩ
analog supply voltage for output buffer AY
analog luminance Y output
analog ground for output buffer AY
analog supply voltage for output buffer AU
analog (B-Y) or
−(B-Y)
output
analog ground for output buffer AU
analog ground for output buffer AV
analog (R-Y) or
−(R-Y)
output
analog supply voltage for output buffer AV
analog ground
analog input
analog input
analog input
analog input
analog supply
analog input
analog supply
analog output
analog ground
analog supply
analog output
analog ground
analog ground
analog output
supply
July 1994
5
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