The pin arrangement and definition of this product meets SFP MSA. Table 1 lists the pin description.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
VeeT
TX Fault
TX Disable
MOD-DEF2
MOD-DEF1
MOD-DEF0
Rate Select
LOS
VeeR
VeeR
VeeR
RD-
RD+
VeeR
VccR
VccT
VeeT
TD+
TD-
VeeT
Function/Description
Transmitter Ground
Transmitter Fault Indication
Transmitter Disable - Module disables on high or open
Module Definition 2 - Two wire serial ID interface
Module Definition 1 - Two wire serial ID interface
Module Definition 0 - Grounded in module
Not Connected
Loss of Signal
Receiver Ground
Receiver Ground
Receiver Ground
Inverse Received Data Out
Received Data Out
Receiver Ground
Receiver Power - 3.3 V ±5%
Transmitter Power - 3.3 V ±5%
Transmitter Ground
Transmitter Data In
Inverse Transmitter Data In
Transmitter Ground
MSA Notes
Note 1
Note 2
Note 3
Note 3
Note 3
Note 4
Note 5
Note 5
Note 5
Note 6
Note 6
Note 5
Note 7
Note 7
Note 5
Note 8
Note 8
Note 5
Notes:
1. TX Fault is an open collector/drain output which should be pulled up externally with a 4.7K – 10 KW resistor on the host board to a supply < Vcc + 0.3
V. When high, this output indicates a laser fault of some kind. Low indicates normal operation. In the low state, the output will be pulled to < 0.8 V.
2. TX disable input is used to shut down the laser output per the state table below with an external 4.7-10 KW4 pull-up resistor.
Low (0 – 0.8 V):
Transmitter on
Between (0.8 V and 2.0 V): Undefined
High (2.0 – 3.465 V):
Transmitter Disabled
Open:
Transmitter Disabled
3. Mod-Def0,1,2. These are the module definition pins. They should be pulled up with a 4.7-10 KW resistor on the host board to a supply less than VccT
(0.3 V or VccR + 0.3 V.
Mod-Def 0 is grounded by the module to indicate that the module is present
Mod-Def 1 is clock line of two wire serial interface for optional serial ID
Mod-Def 2 is data line of two wire serial interface for optional serial ID
4. LOS (Loss of Signal) is an open collector/drain output which should be pulled up externally with a 4.7K – 10 KW resistor on the host board to a supply
< VccT,R + 0.3 V. When high, this output indicates the received optical power is below the worst case receiver sensitivity (as defined by the standard
in use). Low indicates normal operation. In the low state, the output will be pulled to < 0.8 V. Please see later section for LOS timing.
5. VeeR and VeeT may be internally connected within the SFP module
6. RD-/+: These are the differential receiver outputs. They are ac coupled 100
W
differential lines which should be terminated with 100
W
differential at
the user SERDES. The ac coupling is done inside the module and is thus not required on the host board. The voltage swing on these lines will be
between 370 and 2000 mV differential (185 – 1000 mV single ended) when properly terminated.
7. VccR and VccT are the receiver and transmitter power supplies. They are defined as 3.1 – 3.5 V at the SFP connector pin. The maximum supply
current is 300 mA.
8. TD-/+: These are the differential transmitter inputs. They are ac coupled differential lines with 100
W
differential termination inside the module. The
ac coupling is done inside the module and is thus not required on the host board. The inputs will accept differential swings of 500 – 2400 mV (250 –
1200 mV single ended).
4
Serial Identification (EEPROM)
identification protocol. This
The HFCT-5760TL/TP is
protocol uses the 2-wire serial
compliant with the SFP MSA,
CMOS E2PROM protocol of the
which defines the serial
ATMEL AT24C01A or similar.
Table 2. EEPROM Serial ID Memory Contents
Addr
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
MSA compliant, example
contents of the HFCT-5760TL/
TP serial ID memory are defined
in Table 2.
ASCII
Addr
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
Hex
03
04
07
00
00
02
00
00
00
00
00
03
02
00
0F
96
00
00
00
00
41
47
49
4C
45
4E
54
20
20
20
20
20
20
20
20
20
00
00
30
D3
ASCII
Addr
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
Hex
48
46
43
54
2D
35
37
36
30
54
20
20
20
20
20
20
20
20
20
20
00
00
00
99, Note 3
00
1A
00
00
ASCII
H
F
C
T
-
5
7
6
0
T
Addr
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
Hex
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 1
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
00
00
00
Note 3
Hex
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
ASCII
A
G
I
L
E
N
T
60
61
62
63
64
65
66
67
5
Notes:
1. Address 68-83 specify a unique identifier.
2. Address 84-91 specify the date code.
3. Addresses 63 and 95 are check sums. Address 63 is the check sum for bytes 0-62 and address 95 is the check sum for bytes 64-94.