HT46R23/HT46C23
A/D Type 8-Bit MCU
Features
·
Operating voltage:
·
Up to 0.5ms instruction cycle with 8MHz system clock
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
·
23 bidirectional I/O lines (max.)
·
1 interrupt input shared with an I/O line
·
16-bit programmable timer/event counter with
at V
DD
=5V
·
8-level subroutine nesting
·
8 channels 10-bit resolution A/D converter
·
2-channel 8-bit PWM output shared with two I/O lines
·
Bit manipulation instruction
·
15-bit table read instruction
·
63 powerful instructions
·
All instructions in one or two machine cycles
·
Low voltage reset function
·
I
2
C Bus (slave mode)
·
24/28-pin SKDIP/SOP packages
overflow interrupt and 7-stage prescaler
·
On-chip crystal and RC oscillator
·
Watchdog Timer
·
4096´15 program memory
·
192´8 data memory RAM
·
Supports PFD for sound generation
·
HALT function and wake-up feature reduce power
consumption
General Description
The HT46R23/HT46C23 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors. The mask
version HT46C23 is fully pin and functionally compatible
with the OTP version HT46R23 device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, I
2
C interface, HALT and
wake-up functions, enhance the versatility of these de-
vices to suit a wide range of A/D application possibilities
such as sensor signal processing, motor driving, indus-
trial control, consumer products, subsystem controllers,
etc.
I
2
C is a trademark of Philips Semiconductors.
Rev. 1.60
1
May 3, 2004
HT46R23/HT46C23
Block Diagram
P A 5 /IN T
In te rru p t
C ir c u it
S T A C K
P ro g ra m
R O M
P ro g ra m
C o u n te r
IN T C
T M R C
T M R
M
U
P r e s c a le r
X
P A 4 /T M R
f
S
Y S
P A 3 /P F D
P A 4
f
S
Y S
/4
In s tr u c tio n
R e g is te r
M P
M
U
X
D A T A
M e m o ry
P W
W D T
P r e s c a le r
M
P o rt D
W D T
M
U
X
R C
O S C
M 1
P D C
P D
In s tr u c tio n
D e c o d e r
A L U
T im in g
G e n e ra to r
S h ifte r
P A 3 , P A 5
M U X
P D 0 /P W
M 0 ~ P D 1 /P W
8 -C h a n n e l
A /D C o n v e rte r
S T A T U S
P B C
P B
P o rt B
P B 0 /A N 0 ~ P B 7 /A N 7
P A
P A
P A
P A
P A
P A
0 ~ P
3 /P
4 /T
5 /IN
6 /S
7 /S
A 2
F D
M R
T
D A
C L
P A C
O S C 2
O S
R E
V D
V S
S
S
D
C 1
P o rt A
A C C
L V R
P A
I
2
C B u s
S la v e M o d e
P C
P C C
P o rt C
P C 0 ~ P C 4
Pin Assignment
P B 5 /A N 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
P B 4 /A N 4
P B 5 /A N 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
P B 4 /A N 4
P A 3 /P F D
P A 2
P A 1
P A 0
P B 3 /A N 3
P B 2 /A N 2
P B 1 /A N 1
P B 0 /A N 0
V S S
P C 0
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
P B 6 /A N 6
P B 7 /A N 7
P A 4 /T M R
P A 5 /IN T
P A 6 /S D A
P A 7 /S C L
O S C 2
O S C 1
V D D
R E S
P D 0 /P W M 0
P C 1
P A 3 /P F D
P A 2
P A 1
P A 0
P B 3 /A N 3
P B 2 /A N 2
P B 1 /A N 1
P B 0 /A N 0
V S S
P C 0
P C 1
P C 2
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
P B 6 /A N 6
P B 7 /A N 7
P A 4 /T M R
P A 5 /IN T
P A 6 /S D A
P A 7 /S C L
O S C 2
O S C 1
V D D
R E S
P D 1 /P W M 1
P D 0 /P W M 0
P C 4
P C 3
H T 4 6 R 2 3 /H T 4 6 C 2 3
2 4 S K D IP -A /S O P -A
H T 4 6 R 2 3 /H T 4 6 C 2 3
2 8 S K D IP -A /S O P -A
Rev. 1.60
2
May 3, 2004
HT46R23/HT46C23
Pad Assignment
HT46C23
P A 4 /T M R
P A 6 /S D A
P A 3 /P F D
P B 4 /A N 4
P B 5 /A N 5
P B 6 /A N 5
P B 7 /A N 7
P A 5 /IN T
P A 1
3 3
P A 2
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
P A 0
P B 3 /A N 3
P B 2 /A N 2
P B 1 /A N 1
4
5
2 1
1 9
V S S
V S S
7
6
8
9
1 0
1 1
1 2
1 3
1 4
1 5
2 0
1 8
1 7
1 6
P B 0 /A N 0
3
1
2
2 2
P A 7 /S C L
O S C 2
(0 , 0 )
O S C 1
V D D
V D D
T E S T 3
T E S T 2
T E S T 1
* The IC substrate should be connected to VSS in the PCB layout artwork.
P C 0
P C 1
P C 2
P C 3
P C 4
P D 0 /P W M 0
R E S
P D 1 /P W M 1
Pad Description
Pad Name
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6/SDA
PA7/SCL
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
PC0~PC4
I/O
Option
Description
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by options. Software instructions determine the CMOS output or
Pull-high
Schmitt trigger input with or without pull-high resistor (determined by
Wake-up
pull-high options: bit option). The PFD, TMR and INT are pin-shared with
PA3 or PFD
I/O or Serial Bus PA3, PA4 and PA5, respectively. Once the I
2
C Bus function is used, the in-
ternal registers related to PA6 and PA7 can not be used.
I/O
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
mined by pull-high: port option) or A/D input.
Once a PB line is selected as an A/D input (by using software control), the
I/O function and pull-high resistor are disabled automatically.
I/O
Pull-high
Bidirectional 5-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
mine by pull-high option: port option).
Rev. 1.60
3
May 3, 2004
HT46R23/HT46C23
Pad Name
PD0/PWM0
PD1/PWM1
RES
VDD
VSS
OSC1
OSC2
TEST1
TEST2
TEST3
I/O
Option
Pull-high
I/O or PWM
¾
¾
¾
Crystal
or RC
Description
Bidirectional 2-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (de-
termined by pull-high option: port option). The PWM0/PWM1 output func-
tion are pin-shared with PD0/PD1 (dependent on PWM options).
Schmitt trigger reset input. Active low.
Positive power supply
Negative power supply, ground.
OSC1, OSC2 are connected to an RC network or a Crystal (determined by
options) for the internal system clock. In the case of RC operation, OSC2 is
the output terminal for 1/4 system clock.
TEST mode input pin.
It disconnects in normal operation.
I/O
I
¾
¾
I
O
I
¾
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V
to V
SS
+6.0V
Input Voltage..............................V
SS
-0.3V
to V
DD
+0.3V
Storage Temperature ............................-50°C to 125°C
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under
²Absolute
Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Test Conditions
Symbol
Parameter
V
DD
V
DD
Operating Voltage
Operating Current
(Crystal OSC)
Operating Current
(RC OSC)
Operating Current
Standby Current
(WDT Enabled)
Standby Current
(WDT Disabled)
Input Low Voltage for I/O Ports,
TMR and INT
Input High Voltage for I/O Ports,
TMR and INT
Input Low Voltage (RES)
Input High Voltage (RES)
¾
¾
3V
5V
3V
5V
5V
3V
No load, system HALT
5V
3V
No load, system HALT
5V
¾
¾
¾
¾
¾
¾
¾
¾
Conditions
f
SYS
=4MHz
f
SYS
=8MHz
No load, f
SYS
=4MHz
ADC disable
No load, f
SYS
=4MHz
ADC disable
No load, f
SYS
=8MHz
ADC disable
2.2
3.3
¾
¾
¾
¾
¾
¾
¾
¾
¾
0
0.7V
DD
0
0.9V
DD
¾
¾
0.6
2
0.8
2.5
3
¾
¾
¾
¾
¾
¾
¾
¾
5.5
5.5
1.5
4
1.5
4
5
5
10
1
2
0.3V
DD
V
DD
0.4V
DD
V
DD
Min.
Typ.
Max.
Ta=25°C
Unit
V
V
mA
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
I
DD1
I
DD2
I
DD3
I
STB1
I
STB2
V
IL1
V
IH1
V
IL2
V
IH2
Rev. 1.60
4
May 3, 2004
HT46R23/HT46C23
Test Conditions
Symbol
V
LVR
I
OL
Parameter
V
DD
Low Voltage Reset
I/O Port Sink Current
5V
I
OH
3V
I/O Port Source Current
5V
R
PH
V
AD
E
AD
I
ADC
3V
Pull-high Resistance
5V
A/D Input Voltage
A/D Conversion Error
Additional Power Consumption
if A/D Converter is Used
¾
¾
3V
5V
¾
3V
Conditions
¾
V
OL
=0.1V
DD
V
OL
=0.1V
DD
V
OH
=0.9V
DD
V
OH
=0.9V
DD
¾
¾
¾
¾
¾
2.7
4
10
-2
-5
20
10
0
¾
¾
¾
3
8
20
-4
-10
60
30
¾
±0.5
0.5
1.5
3.3
¾
¾
¾
¾
100
50
V
DD
±1
1
3
V
mA
mA
mA
mA
kW
kW
V
LSB
mA
mA
Min.
Typ.
Max.
Unit
A.C. Characteristics
Test Conditions
Symbol
Parameter
V
DD
f
SYS
System Clock
Timer I/P Frequency
(TMR)
Watchdog Oscillator Period
5V
t
RES
t
SST
t
INT
t
AD
t
ADC
t
ADCS
t
IIC
External Reset Low Pulse Width
System Start-up Timer Period
Interrupt Pulse Width
A/D Clock Period
A/D Conversion Time
A/D Sampling Time
I
2
C Bus Clock Period
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
3V
Conditions
2.2V~5.5V
3.3V~5.5V
2.2V~5.5V
3.3V~5.5V
¾
¾
¾
Wake-up from HALT
¾
¾
¾
¾
Connect to external
pull-high resistor 2kW
400
400
0
0
45
32
1
¾
1
1
¾
¾
64
¾
¾
¾
¾
90
65
¾
1024
¾
¾
76
32
¾
4000
8000
4000
8000
180
130
¾
¾
¾
¾
¾
¾
¾
Min.
Typ.
Max.
Ta=25°C
Unit
kHz
kHz
kHz
kHz
ms
ms
ms
*t
SYS
ms
ms
t
AD
t
AD
*t
SYS
f
TIMER
t
WDTOSC
Note: *t
SYS
=1/f
SYS
Rev. 1.60
5
May 3, 2004
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