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70V07S55G

Description
PGA-68, Tray
Categorystorage   
File Size511KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
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70V07S55G Overview

PGA-68, Tray

70V07S55G Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codePGA
package instructionPGA, PGA68,11X11
Contacts68
Manufacturer packaging codeGU68
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys Confidence4
Samacsys StatusReleased
Samacsys PartID11321109
Samacsys Pin Count68
Samacsys Part CategoryIntegrated Circuit
Samacsys Package CategoryOther
Samacsys Footprint NameGU68_1
Samacsys Released Date2020-02-02 18:27:45
Is SamacsysN
Maximum access time55 ns
Other featuresINTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O typeCOMMON
JESD-30 codeS-CPGA-P68
JESD-609 codee0
length29.464 mm
memory density262144 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals68
word count32768 words
character code32000
Operating modeASYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize32KX8
Output characteristics3-STATE
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Encapsulate equivalent codePGA68,11X11
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Certification statusNot Qualified
Maximum seat height5.207 mm
Maximum standby current0.006 A
Minimum standby current3 V
Maximum slew rate0.14 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formPIN/PEG
Terminal pitch2.54 mm
Terminal locationPERPENDICULAR
Maximum time at peak reflow temperatureNOT SPECIFIED
width29.464 mm
Base Number Matches1
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
Features
70V07S/L
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 25/35/55ns (max.)
– Industrial: 35ns (max.)
Low-power operation
– IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V07L
Active: 300mW (typ.)
Standby: 660
μ
W (typ.)
Interrupt Flag
IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = V
IH
for
BUSY
output flag on Master
M/S = V
IL
for
BUSY
input on Slave
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and a 80-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OE
L
CE
L
R/W
L
OE
R
CE
R
R/W
R
I/O
0L
- I/O
7L
I/O
Control
BUSY
L
(1,2)
I/O
Control
I/O
0R
-I/O
7R
,
BUSY
R
Address
Decoder
15
(1,2)
A
14L
A
0L
MEMORY
ARRAY
15
Address
Decoder
A
14R
A
0R
CE
L
OE
L
R/W
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
and
INT
outputs are non-tri-stated push-pull.
M/S
SEM
R
INT
R(2)
2943 drw 01
JULY 2019
1
DSC 2943/11
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