M I C
of Crystek Corporation
ROWAVE
A Division
CPLL58-2175-2175
0.582"
×
0.800" SMD
Features
2.175 GHz
Standard 3 Wire Interface
Small layout 0.582"
×
0.8"
Applications
Digital Radio Equipment
Fixed Wireless Access
Satellite Communications Systems
Base Stations
Personal Communications Systems
Portable Radios
Test Instruments
Wireless Infrastructure
The CPLL58 is a complete PLL/Synthesizer needing only an external frequency reference and supply
voltages for the internal PLL (phase lock loop) and VCO (voltage controlled oscillator). The Crystek
CPLL58 is programmed using a standard three line interface (Data, Clock and Load Enable).
The CPLL58 family has been initially released to cover 1 GHz to 5 GHz in bands. It is housed in a
compact 0.582-in.
×
0.8-in.
×
0.15-in. SMD package which saves board space. Typical phase noise at
4 GHz is -90 dBc/Hz at 10 kHz offset with 0 dBm minimum output power.
Rev D
Page 1 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M I C
of Crystek Corporation
ROWAVE
A Division
PERFORMANCE SPECIFICATION
Frequency Range:
Step Size:
Settling Time,
to within ± 1kHz (Freq. step < 25MHz):
Output Power:
Output Phase Noise: (See Plot Below)
@1kHz offset
@10kHz offset
@100kHz offset
@1MHz offset
Power Supply:
V1=VCO Supply
V2=PLL Supply
Supply Current:
I1=VCO Input Current
I2=PLL Input Current
Spurious Suppression
PFDSpur
Reference Feedthru
Harmonic Suppression:
2
nd
Reference Frequency
RF Output Level
Input Reference Level
Input Impedance
RF Output Impedance
Operating Temperature Range:
Logic Inputs (Clock, Data, and LE):
Input “High” Voltage
Input “Low” Voltage
Locked Detector (LD):
Locked
Un-Locked
1.4
1.4
-40
-5
0.8
4.75
2.7
0
MIN
CPLL58-2175-2175
0.582"
×
0.800" SMD
TYP
2.175
100
1
+3.0
-75
-95
-120
-145
5.0
3.0
50
25
-70
-80
-15
10
0
100k
50
MAX
UNITS
GHz
kHz
msec
+6.0
-70
-90
-115
-140
5.25
3.3
dBm
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Volts
Volts
mA
mA
dBc
-60
-70
-10
+5
V2
dBc
dBc
dBc
MHz
dBm
Vp-p
Ohm
Ohm
+85
°C
0.6
Volts
Volts
0.4
Volts
Rev D
Page 2 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M I C
of Crystek Corporation
ROWAVE
A Division
CPLL58-2175-2175
0.582"
×
0.800" SMD
Rev D
Page 3 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M I C
of Crystek Corporation
ROWAVE
A Division
CPLL58-2175-2175
0.582"
×
0.800" SMD
TOP VIEW
0.800
0.600
0.520
0.440
0.360
0.280
0.200
0.00
BOTTOM VIEW
V2 [Pin1]
GND
GND
0.00
GND
REF
V1
CRYSTEK
CPLL58
2175-2175
YYWW
0.171
0.251
0.331
0.411
GND
GND
GND
GND
GND
GND
GND
GND
LE
= Load Enable, CMOS Input
DATA = Serial Data Input
CLK = Clock
LD
= Lock Detect
REF = Reference Input
V1
= Analog Supply Input (VCO)
V2
= Digital Supply Input (PLL)
RF
= RF Output
DATA
0.582
LE
GND
CLK
TOP ORIENTATION MARK
0.150
0.000
0.052
0.000
0.000
Ramp-Up
3°C/Sec Max.
0.052
Pad Detail
RECOMMENDED REFLOW SOLDERING PROFILE
Critical Temperature Zone
Ramp-Down
6°C/Sec.
260°C
TEMPERATURE
217°C
200°C
150°C
Preheat
180 Secs. Max.
8 Minutes Max.
RF
LD
90 Secs. Max.
260°C for
10 Secs. Max.
Rev D
Page 4 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
M I C
of Crystek Corporation
ROWAVE
A Division
CPLL58-2175-2175
0.582"
×
0.800" SMD
ENVIRONMENTAL COMPLIANCE
Parameter
Mechanical Shock
Mechanical Vibration
Solderability
Resistance to Solvents
Conditions
MIL-STD-883, Method 2002
MIL-STD-883, Method 2007
MIL-STD-883, Method 1014
MIL-STD-883, Method 2016
Programming Guide for CPLL58-XXXX
Introduction
The CPLL58 uses a simple 3 wire interface to program four internal registers. See Figure 1.
t
3
CLOCK
t
4
t
1
DATA
DB23 (MSB)
DB22
t
2
DB2
DB1(CONTROL
BIT C2)
DB0(LSB)
(CONTROL BIT C1)
t
6
LE
t
5
LE
Figure 1. Timing Diagram
There are four 24 bit registers that need to be programmed. Which register is written into is simply
controlled by Control Bits C1 and C2. Table I summarizes the Truth Table for Control Bits C1 and C2.
Control Bits
C2
C1
0
0
1
1
0
1
0
1
R Counter
N Counter (A and B)
Function Latch (Including Prescaler)
Initialization Latch
Table I. C2, C1 Truth Table
Data Latch
Rev D
Page 5 of 7
CRYSTEK
CORPORATION
12730 Commonwealth Drive • Fort Myers, Florida 33913
Phone: 239-561-3311 • 800-237-3061
Fax: 239-561-1025 • www.crystek.com
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