7007S25J datasheet, PDF - EEWORLD Datasheet

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7007S25J: DescriptionPLCC-68, Tube; Categorystorage; File Size485KB，23 Pages; ManufacturerIDT (Integrated Device Technology)

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7007S25J Overview

PLCC-68, Tube

7007S25J Parametric

Parameter Name	Attribute value
Brand Name	Integrated Device Technology
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	PLCC
package instruction	0.950 X 0.950 INCH, 0.170 INCH HEIGHT, PLASTIC, LCC-68
Contacts	68
Manufacturer packaging code	PL68
Reach Compliance Code	not_compliant
ECCN code	EAR99
Is Samacsys	N
Maximum access time	25 ns
Other features	INTERRUPT FLAG; SEMAPHORE; AUTOMATIC POWER-DOWN
I/O type	COMMON
JESD-30 code	S-PQCC-J68
JESD-609 code	e0
length	24.2062 mm
memory density	262144 bit
Memory IC Type	DUAL-PORT SRAM
memory width	8
Humidity sensitivity level	1
Number of functions	1
Number of ports	2
Number of terminals	68
word count	32768 words
character code	32000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	32KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Encapsulate equivalent code	LDCC68,1.0SQ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	5 V
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum standby current	0.015 A
Minimum standby current	4.5 V
Maximum slew rate	0.305 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	24.2062 mm
Base Number Matches	1

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HIGH-SPEED

32K x 8 DUAL-PORT

STATIC RAM

Features

◆

7007L

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

– Commercial: 15ns (max.)

– Industrial: 20ns (max.)

Low-power operation

– IDT7007L

Active: 850mW (typ.)

Standby: 1mW (typ.)

IDT7007 easily expands data bus width to 16 bits or more

using the Master/Slave select when cascading more than

one device

◆

M/S = H for

BUSY

output flag on Master,

M/S = L for

BUSY

input on Slave

Interrupt Flag

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in a 68-pin PLCC and a 80-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Green parts available, see ordering information

Functional Block Diagram

R/W

I/O

- I/O

I/O

Control

BUSY

14L

(1,2)

I/O

-I/O

I/O

Control

BUSY

14R

(1,2)

Address

Decoder

MEMORY

ARRAY

Address

Decoder

R/W

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

R/W

SEM

(2)

INT

M/S

SEM

INT

(2)

2940 drw 01

NOTES:

1. (MASTER):

BUSY

is output; (SLAVE):

BUSY

is input.

BUSY

and

INT

outputs are non-tri-stated push-pull.

SEPTEMBER 2019

DSC 2940/16

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