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7008L35GGB8

Description
Dual-Port SRAM
Categorystorage   
File Size230KB,20 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

7008L35GGB8 Overview

Dual-Port SRAM

7008L35GGB8 Parametric

Parameter NameAttribute value
MakerIDT (Integrated Device Technology)
package instructionPGA,
Reach Compliance Codecompliant
Is SamacsysN
Maximum access time35 ns
JESD-30 codeS-CPGA-P108
memory density524288 bit
Memory IC TypeDUAL-PORT SRAM
memory width8
Number of functions1
Number of terminals108
word count65536 words
character code64000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize64KX8
Package body materialCERAMIC, METAL-SEALED COFIRED
encapsulated codePGA
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Filter levelMIL-PRF-38535
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyCMOS
Temperature levelMILITARY
Terminal formPIN/PEG
Terminal locationPERPENDICULAR
Base Number Matches1
HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
Features
IDT7008S/L
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/55ns (max.)
– Military: 25/35/55ns (max.)
Low-power operation
– IDT7008S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7008L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Dual chip enables allow for depth expansion without
external logic
IDT7008 easily expands data bus width to 16 bits or
more using the Master/Slave select when cascading more
than one device
M/S = V
IH
for
BUSY
output flag on Master,
M/S = V
IL
for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
CE
0L
CE
1L
OE
L
R/W
R
CE
0R
CE
1R
OE
R
I/O
0-7L
I/O
Control
I/O
Control
I/O
0-7R
BUSY
L
A
15L
A
0L
(1,2)
BUSY
R
64Kx8
MEMORY
ARRAY
7008
16
16
(1,2)
Address
Decoder
Address
Decoder
A
15R
A
0R
CE
0L
CE
1L
OE
L
R/W
L
SEM
L
(2)
INT
L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0R
CE
1R
OE
R
R/W
R
SEM
R
(2)
INT
R
3198 drw 01
M/S
(1)
NOTES:
1.
BUSY
is an input as a Slave (M/S = V
IL
) and an output when it is a Master (M/S = V
IH
).
2.
BUSY
and
INT
are non-tri-state totem-pole outputs (push-pull).
OCTOBER 2014
DSC 3198/10
1
©2014 Integrated Device Technology, Inc.
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