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70V5388S166BGG8

Description
Multi-Port SRAM, 64KX18, 3.2ns, CMOS, PBGA272
Categorystorage   
File Size248KB,29 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance  
Download Datasheet Parametric View All

70V5388S166BGG8 Overview

Multi-Port SRAM, 64KX18, 3.2ns, CMOS, PBGA272

70V5388S166BGG8 Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
package instructionBGA-272
Reach Compliance Codecompliant
Is SamacsysN
Maximum access time3.2 ns
Maximum clock frequency (fCLK)166 MHz
I/O typeCOMMON
JESD-30 codeS-PBGA-B272
JESD-609 codee3
memory density1179648 bit
Memory IC TypeFOUR-PORT SRAM
memory width18
Number of functions1
Number of ports4
Number of terminals272
word count65536 words
character code64000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64KX18
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA272,20X20,50
Package shapeSQUARE
Package formGRID ARRAY
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Maximum standby current0.015 A
Minimum standby current3.15 V
Maximum slew rate0.395 mA
Maximum supply voltage (Vsup)3.45 V
Minimum supply voltage (Vsup)3.15 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
Base Number Matches1
3.3V 64/32K X 18
SYNCHRONOUS
FOURPORT™ STATIC RAM
Features
IDT70V5388/78
True four-ported memory cells which allow simultaneous
access of the same memory location
Synchronous Pipelined device
– 64/32K x 18 organization
Pipelined output mode allows fast 200MHz operation
High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x
4 ports)
LVTTL I/O interface
High-speed clock to data access 3.0ns (max.)
3.3V Low operating power
Interrupt flags for message passing
Width and depth expansion capabilities
Counter readback on address lines
R/
W
P1
U B
P1
C E
0P1
CE
1P1
L B
P1
O E
P1
Counter wrap-around control
– Internal mask register controls counter wrap-around
– Counter-Interrupt flags to indicate wrap-around
Mask register readback on address lines
Global Master reset for all ports
Dual Chip Enables on all ports for easy depth expansion
Separate upper-word and lower-word controls on all ports
272-BGA package (27mm x 27mm 1.27mm ball pitch) and
256-BGA package (17mm x 17mm 1.0mm ball pitch)
Commercial and Industrial temperature ranges
JTAG boundary scan
MBIST (Memory Built-In Self Test) controller
Green parts available, see ordering information
Port - 1 Logic Block Diagram
(2)
0
1
1 /0
I/O
9P1
- I/O
17P1
I/O
0P1
- I/O
8P1
Port 1
I/O
Control
TR S T
TMS
TCK
TDI
CLKMBIST
JTAG
Controller
MBIST
TDO
Addr.
Read
Back
Port 1
Readback
Register
MRST
A
0P1
- A
15P1
(1)
C N T R D
P1
M K R D
P1
M K L D
P1
C N T IN C
P1
C N T L D
P1
C N T R S T
P1
CLK
P1
MRST
C N T IN T
P1
Port 1
Mask
Register
Priority
Decision
Logic
Port 1
Counter/
Address
Register
Port 1
Address
Decode
64KX18
Memory
Array
,
R/
W
P1
C E
0P1
CE
1P1
CLK
P1
Port 1
Interrupt
Logic
IN T
P1
MRST
NOTE:
1. A
15
x is a NC for IDT70V5378.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
5649 drw 01
JANUARY 2006
DSC-5649/4
1
©2006 Integrated Device Technology, Inc.
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