EMRA42P2H-24.576M TR
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on May 31, 2018)
174 SVHC
ITEM DESCRIPTION
MEMS Clock Oscillators LVCMOS (CMOS) 2.5Vdc 4 Pad 2.0mm x 2.5mm Plastic Surface Mount (SMD)
24.576MHz ±50ppm over -40°C to +105°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
Aging at 25°C
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Output Control Function
Output Control Input Voltage Logic
High (Vih)
Output Control Input Voltage Logic
Low (Vil)
Tri-State Output Enable Time
Tri-State Output Disable Time
Period Jitter (RMS)
RMS Phase Jitter (Fj = 900kHz to
7.5MHz; Random)
RMS Phase Jitter (Fj = 12kHz to
20MHz; Random)
Start Up Time
Storage Temperature Range
24.576MHz
±50ppm Maximum over -40°C to +105°C (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability
over the Operating Temperature Range, Supply Voltage Change, and Output Load Change)
±1.5ppm Maximum First Year
2.5Vdc ±10%
6mA Maximum (No Load)
90% of Vdd Minimum (IOH = -3mA)
10% of Vdd Maximum (IOL = +3mA)
1.2nSec Typical, 3nSec Maximum (Measured from 20% to 80% of waveform)
50 ±5(%) (Measured at 50% of waveform)
15pF Maximum
CMOS
Tri-State (Disabled Output: High Impedance)
70% of Vdd Minimum or No Connect to Enable Output
30% of Vdd Maximum to Disable Output
150nSec Maximum
150nSec Maximum
2pSec Typical, 4pSec Maximum
0.5pSec Typical, 1pSec Maximum
1.5pSec Typical, 3pSec Maximum
5mSec Maximum
-65°C to +150°C
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Flammability
Mechanical Shock
Moisture Sensitivity
Solderability
Temperature Cycling
Vibration
JESD22-A114, HBM, 2000V
UL94-V0
MIL-STD-883, Method 2002, Condition E, 10,000G
J-STD-020, MSL 1
MIL-STD-883, Method 2003 (Four I/O Pads on bottom of package only)
JESD22-A104, Condition B
MIL-STD-883, Method 2007, Condition A, 20G
www.ecliptek.com | Specification Subject to Change Without Notice | Revision D 11/15/2016 | Page 1 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EMRA42P2H-24.576M TR
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
CONNECTION
Tri-State (High
Impedance)
Ground
Output
Supply Voltage
2.00
±0.05
0.85
MAX
4
1
0.50
±0.05 (x4)
2
3
4
2.50
±0.05
1.00
±0.05
3
2
LINE MARKING
1
Ecliptek Manufacturing
Identifier
0.75
±0.05 (x4)
1.10
±0.05
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.00 (X4)
1.10 (X4)
0.80
Solder Land
(X4)
0.50
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Revision D 11/15/2016 | Page 2 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EMRA42P2H-24.576M TR
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
Tri-State or
Power Down
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass
capacitor close (less than 2mm) to the package ground and supply voltage pin is required.
Note 2: A low input capacitance (<12pF), 10X Attentuation Factor, High Impedance (>10Mohms), and
High bandwidth (>300MHz) passive probe is recommended.
Note 3: Capacitance value CL includes sum of all probe and fixture capacitance. See applicable specification sheet
for ‘Load Drive Capability’.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision D 11/15/2016 | Page 4 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
FPGA/CPLD
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