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5V991A-7JG8

Description
PLL Based Clock Driver
Categorylogic    logic   
File Size74KB,8 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric Compare View All

5V991A-7JG8 Overview

PLL Based Clock Driver

5V991A-7JG8 Parametric

Parameter NameAttribute value
package instructionQCCJ,
Reach Compliance Codecompli
series5V
Input adjustmentSTANDARD
JESD-30 codeR-PQCC-J32
Logic integrated circuit typePLL BASED CLOCK DRIVER
Number of functions1
Number of inverted outputs
Number of terminals32
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeRECTANGULAR
Package formCHIP CARRIER
Same Edge Skew-Max(tskwd)0.75 ns
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal formJ BEND
Terminal locationQUAD
Base Number Matches1
IDT5V991A
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
COMMERCIAL AND INDUSTRIAL TEMPERATURE
RANGES
3.3V PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK™
FEATURES:
REF is 5V tolerant
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 85MHz
2x, 4x, 1/2, and 1/4 outputs
3 skew grades:
IDT5V991A-2: t
SKEW0
<250ps
IDT5V991A-5: t
SKEW0
<500ps
IDT5V991A-7: t
SKEW0
<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <200ps peak-to-peak
Available in 32-pin PLCC Package
Not Recommended for New Design
IDT5V991A
NRND
The IDT5V991A is a high fanout 3.3V PLL based clock driver
intended for high performance computing and data-communications
applications. A key feature of the programmable skew is the ability of
outputs to lead or lag the REF input signal. The IDT5V991A has eight
programmable skew outputs in four banks of 2. Skew is controlled by
3-level input signals that may be hard-wired to appropriate HIGH-MID-
LOW levels.
When the GND/sOE pin is held low, all the outputs are synchro-
nously enabled. However, if GND/sOE is held high, all the outputs
except 3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the V
CCQ
/PE is held high, all the outputs are
synchronized with the positive edge of the REF clock input. When
V
CCQ
/PE is held low, all the outputs are synchronized with the negative
edge of REF. Both devices have LVTTL outputs with 12mA balanced
drive outputs.
DESCRIPTION:
FUNCTIONAL BLOCK DIAGRAM
GND/sOE
1Q
0
3
1F1:0
V
CCQ
/PE
Skew
Select
REF
PLL
FB
3
FS
Skew
Select
3
3
3F1:0
Skew
Select
3
3
4F1:0
4Q
0
4Q
1
3Q
0
3Q
1
3
3
2F1:0
2Q
0
2Q
1
1Q
1
Skew
Select
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2013 Integrated Device Technology, Inc.
NOVEMBER 7, 2013
DSC 5963/3

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Description PLL Based Clock Driver PLL Based Clock Driver PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, GREEN, PLASTIC, LCC-32 PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32 PLL Based Clock Driver PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32 PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, GREEN, PLASTIC, LCC-32 PLL Based Clock Driver, 5V Series, 4 True Output(s), 0 Inverted Output(s), PQCC32, PLASTIC, LCC-32 PLL Based Clock Driver PLL Based Clock Driver
Reach Compliance Code compli unknow compli _compli not_compliant not_compliant compliant not_compliant unknown compli
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
package instruction QCCJ, , QCCJ, QCCJ, LDCC32,.5X.6 - QCCJ, LDCC32,.5X.6 QCCJ, QCCJ, LDCC32,.5X.6 , QCCJ,
series 5V - 5V 5V - 5V 5V 5V - 5V
Input adjustment STANDARD - STANDARD STANDARD - STANDARD STANDARD STANDARD - STANDARD
JESD-30 code R-PQCC-J32 - R-PQCC-J32 R-PQCC-J32 - R-PQCC-J32 R-PQCC-J32 R-PQCC-J32 - R-PQCC-J32
Number of functions 1 - 1 1 - 1 1 1 - 1
Number of terminals 32 - 32 32 - 32 32 32 - 32
Actual output times 8 - 4 4 - 4 4 4 - 8
Maximum operating temperature 70 °C - 70 °C 85 °C - 85 °C 70 °C 70 °C - 70 °C
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code QCCJ - QCCJ QCCJ - QCCJ QCCJ QCCJ - QCCJ
Package shape RECTANGULAR - RECTANGULAR RECTANGULAR - RECTANGULAR RECTANGULAR RECTANGULAR - RECTANGULAR
Package form CHIP CARRIER - CHIP CARRIER CHIP CARRIER - CHIP CARRIER CHIP CARRIER CHIP CARRIER - CHIP CARRIER
Same Edge Skew-Max(tskwd) 0.75 ns - 1.2 ns 1.2 ns - 0.7 ns 0.7 ns 0.5 ns - 0.5 ns
Maximum supply voltage (Vsup) 3.6 V - 3.6 V 3.6 V - 3.6 V 3.6 V 3.6 V - 3.6 V
Minimum supply voltage (Vsup) 3 V - 3 V 3 V - 3 V 3 V 3 V - 3 V
Nominal supply voltage (Vsup) 3.3 V - 3.3 V 3.3 V - 3.3 V 3.3 V 3.3 V - 3.3 V
surface mount YES - YES YES - YES YES YES - YES
Temperature level COMMERCIAL - COMMERCIAL INDUSTRIAL - INDUSTRIAL COMMERCIAL COMMERCIAL - COMMERCIAL
Terminal form J BEND - J BEND J BEND - J BEND J BEND J BEND - J BEND
Terminal location QUAD - QUAD QUAD - QUAD QUAD QUAD - QUAD
Base Number Matches 1 1 1 1 1 1 1 1 1 -
Is it Rohs certified? - - conform to incompatible incompatible incompatible conform to incompatible - -
JESD-609 code - - e3 e0 e0 e0 e3 e0 - -
Terminal surface - - MATTE TIN Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) Tin/Lead (Sn85Pb15) MATTE TIN Tin/Lead (Sn85Pb15) - -
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