GS88436B-150 datasheet, PDF - EEWORLD Datasheet

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GS88436B-150: Description512K x 18, 256K x 36 8Mb S/DCD Sync Burst SRAMs; Categorystorage storage; File Size543KB，25 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/

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GS88436B-150 Overview

512K x 18, 256K x 36 8Mb S/DCD Sync Burst SRAMs

GS88436B-150 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	GSI Technology
Parts packaging code	BGA
package instruction	BGA,
Contacts	119
Reach Compliance Code	compli
ECCN code	3A991.B.2.B
Maximum access time	9 ns
Other features	FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B119
JESD-609 code	e0
length	22 mm
memory density	9437184 bi
Memory IC Type	CACHE SRAM
memory width	36
Humidity sensitivity level	3
Number of functions	1
Number of terminals	119
word count	262144 words
character code	256000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX36
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	RECTANGULAR
Package form	GRID ARRAY
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
Maximum seat height	2.4 mm
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN LEAD
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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Preliminary

GS88418/36B-200/180/166/150/133

119-Bump BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipelined

operation

• Single/Dual Cycle Deselect Selectable

• ZQ mode pin for user-selectable high/low output drive strength

• 3.3 V +10%/–5% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Common data inputs and data outputs

• Clock Control, registered, address, data, and control

• Internal self-timed write cycle

• Automatic power-down for portable applications

• 119-bump BGA package

512K x 18, 256K x 36

8Mb S/DCD Sync Burst SRAMs

Flow Through/Pipeline Reads

200 MHz–133 MHz

3.3 V V

3.3 V and 2.5 V I/O

(LBO) input. The Burst function need not be used. New

addresses can be loaded on every cycle with no degradation of

chip performance.

The function of the Data Output register can be controlled by

the user via the FT mode bump (Bump 5R). Holding the FT

mode pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

SCD and DCD Pipelined Reads

The GS88436B is a SCD (Single Cycle Deselect) and DCD

(Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one

stage less than read commands. SCD RAMs begin turning off

their outputs immediately after the deselect command has been

captured in the input registers. DCD RAMs hold the deselect

command for one full cycle and then begin turning off their

outputs just after the second rising edge of clock. The user may

configure this SRAM for either mode of operation using the

SCD mode input on Bump 4L.

Pipeline

3-1-1-1

Flow

Through

2-1-1-1

tCycle

-200

5.0

3.0

450

7.5

270

-180

5. 5

3.2

410

270

-166

6.0

3.5

380

8.5

250

-150

6.7

3.8

350

9.0

240

-133

7.5

4.0

340

9.5

220

Unit

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Functional Description

Applications

The GS88418/36B is a 9,437,184-bit high performance

synchronous SRAM with a 2-bit burst address counter.

Although of a type originally developed for Level 2 Cache

applications supporting high performance CPUs, the device

now finds application in synchronous SRAM applications,

ranging from DSP main store to networking chip set support.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ

low) for multi-drop bus applications and normal drive strength

(ZQ floating or high) point-to-point applications. See the

Output Driver Characteristics chart for details.

Controls

Addresses, data I/Os, chip enables (E1, in x18 version, E1 and

E2 in x36 version), address burst control inputs (ADSP,

ADSC, ADV), and write control inputs (Bx, BW, GW) are

synchronous and are controlled by a positive-edge-triggered

clock input (CK). Output enable (G) and power-down control

(ZZ) are asynchronous inputs. Burst cycles can be initiated

with either ADSP or ADSC inputs. In Burst mode, subsequent

burst addresses are generated internally and are controlled by

ADV. The burst address counter may be configured to count in

either linear or interleave order with the Linear Burst Order

Rev: 1.05 10/2001

1/25

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS884B operates on a 3.3 V power supply and all inputs/

outputs are 3.3 V- and 2.5 V-compatible. Separate output

power (V

DDQ

) pins are used to decouple output noise from the

internal circuit.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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