GS8662S09GE-333 datasheet, PDF

Datasheet> All Categories > storage> storage> GS8662S09GE-333

GS8662S09GE-333: Description72Mb Burst of 2 DDR SigmaSIO-II SRAM; Categorystorage storage; File Size950KB，37 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

Download Datasheet Parametric View All

GS8662S09GE-333 Overview

72Mb Burst of 2 DDR SigmaSIO-II SRAM

GS8662S09GE-333 Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	LBGA,
Contacts	165
Reach Compliance Code	unknow
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	75497472 bi
Memory IC Type	DDR SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX9
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

Preview

Download Datasheet

View All

Preliminary

GS8662S08/09/18/36E-333/300/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaSIO™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• DLL circuitry for wide output data valid window and future

frequency scaling

• Burst of 2 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb Burst of 2

DDR SigmaSIO-II SRAM

333 MHz–167 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

JEDEC Std. MO-216, Variation CAB-1

SigmaRAM™ Family Overview

GS8662S08/09/18/36 are built in compliance with the

SigmaSIO-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. These are the first in a family of wide, very low

voltage HSTL I/O SRAMs designed to operate at the speeds

needed to implement economical high performance

networking systems.

Clocking and Addressing Schemes

A Burst of 2 SigmaSIO-II SRAM is a synchronous device. It

employs dual input register clock inputs, K and K. The device

also allows the user to manipulate the output register clock

input quasi independently with dual output register clock

inputs, C and C. If the C clocks are tied high, the K clocks are

routed internally to fire the output registers instead. Each Burst

of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs,

CQ and CQ, which are synchronized with read data output.

When used in a source synchronous clocking scheme, the Echo

Clock outputs can be used to fire input registers at the data’s

destination.

Because Separate I/O Burst of 2 RAMs always transfer data in

two packets, A0 is internally set to 0 for the first read or write

transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a Burst of 2 RAM is always one address pin less than

the advertised index depth (e.g., the 4M x 18 has a 1M

addressable index).

Parameter Synopsis

- 333

tKHKH

tKHQV

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.5 ns

Rev: 1.01 9/2005

1/37

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Recommended Resources

Shanling brand BYD-165, BYD-180 refrigerator circuit

RP5020 series typical application circuit diagram

Power line interface and FSK demodulation circuit

Automatic charger circuit with manual trigger function

Ultra high impedance amplifier circuit

Computer motherboard circuit diagram 820 1_17

[Learn Power from TI] Series --- Share a single lithium battery charging management chip: Main features of the chip: BQ24032A -------- 1.5A single lithium battery charging management chip Chip information reading: [url=http://www.ti.com.cn/cn/lit/ds/symlink/bq24032a.pdf][color=#810081]http...; qwqwqw2088 Analogue and Mixed Signal

How to solve the problem of empty drop-down list when selecting a tool when building bootrom (newbie): Refer to > http://blog.chinaunix.net/u/21277/showart_212603.html and found several problems. The config folder of AMD's PC-NET driver is pc486.972 instead of pcPentium after decompression, and CPU==I8...; ifare Embedded System

About upgrading from wince5.0 to wince6.0: The platform I am using now is pxa270+wince5.0. My boss asked me to upgrade to wince6.0. I have never done porting before, and I did not write the original 5.0 code. I took on this job with all my hea...; guoyaru123 Embedded System

Firmware Download | In-depth evaluation of the Flink OK3568-C development board: conclusions revealed: Development Environment: Host: Ubuntu 18.04 Development board: OK3568-C development board Feiling embedded OK3568-C development board can use USB OTG burning and TF card burning, among which USB OTG i...; 小螃蟹呀 ARM Technology

pic18f2550 TMR0 high 8 bits do not count automatically: [table=98%,rgb(238, 238, 238)] [tr][td]Hello everyone, I used pic18f2550 to make an electronic clock, and used TMR0 timing interrupt. After I assigned initial values to TMR0L and TMR0H, only TMR0L cou...; csliu911 Microchip MCU

Help: msp430 serial communication problem: When using the serial port of msp430 for communication, I can send and receive but the code is garbled when using the emulator and the special debugging tool at the same time.The baud rate is obtained...; chen_jia_ Microcontroller MCU

Shortcut: A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ

Popular Components