GS8662D09GE-333I datasheet, PDF

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GS8662D09GE-333I: Description72Mb SigmaQuad-II Burst of 4 SRAM; Categorystorage storage; File Size886KB，29 Pages; ManufacturerGSI Technology; Websitehttp://www.gsitechnology.com/; Environmental Compliance

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GS8662D09GE-333I Overview

72Mb SigmaQuad-II Burst of 4 SRAM

GS8662D09GE-333I Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	GSI Technology
Parts packaging code	BGA
package instruction	15 X 17 MM, 1 MM PITCH, ROHS COMPLIANT, FPBGA-165
Contacts	165
Reach Compliance Code	compli
ECCN code	3A991.B.2.B
Maximum access time	0.45 ns
Other features	PIPELINED ARCHITECTURE
Maximum clock frequency (fCLK)	333 MHz
I/O type	SEPARATE
JESD-30 code	R-PBGA-B165
JESD-609 code	e1
length	17 mm
memory density	75497472 bi
Memory IC Type	DDR SRAM
memory width	9
Humidity sensitivity level	3
Number of functions	1
Number of terminals	165
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	8MX9
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA165,11X15,40
Package shape	RECTANGULAR
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	260
power supply	1.5/1.8,1.8 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum standby current	0.31 A
Minimum standby current	1.7 V
Maximum slew rate	0.975 mA
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Silver/Copper (Sn/Ag/Cu)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	NOT SPECIFIED
width	15 mm

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Preliminary

GS8662D08/09/18/36E-333/300/250/200/167

165-Bump BGA

Commercial Temp

Industrial Temp

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 4 Read and Write

• 1.8 V +100/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• Pin-compatible with present 9Mb, 18Mb, and 36Mb and

future 144Mb devices

• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package

• RoHS-compliant 165-bump BGA package available

72Mb SigmaQuad-II

Burst of 4 SRAM

333 MHz–167 MHz

1.8 V V

1.8 V and 1.5 V I/O

Bottom View

165-Bump, 15 mm x 17 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

C clock inputs. C and C are also independent single-ended

clock inputs, not differential inputs. If the C clocks are tied

high, the K clocks are routed internally to fire the output

registers instead.

Because Separate I/O SigmaQuad-II B4 RAMs always transfer

data in four packets, A0 and A1 are internally set to 0 for the

first read or write transfer, and automatically incremented by 1

for the next transfers. Because the LSBs are tied off internally,

the address field of a SigmaQuad-II B4 RAM is always two

address pins less than the advertised index depth (e.g., the 4M

x 18 has a 1024K addressable index).

SigmaQuad™ Family Overview

The GS8662D08/09/18/36E are built in compliance with the

SigmaQuad-II SRAM pinout standard for Separate I/O

synchronous SRAMs. They are 75,497,472-bit (72Mb)

SRAMs. The GS8662D08/18/36E SigmaQuad SRAMs are

just one element in a family of low power, low voltage HSTL

I/O SRAMs designed to operate at the speeds needed to

implement economical high performance networking systems.

Clocking and Addressing Schemes

The GS8662D08/09/18/36E SigmaQuad-II SRAMs are

synchronous devices. They employ two input register clock

inputs, K and K. K and K are independent single-ended clock

inputs, not differential inputs to a single differential clock input

buffer. The device also allows the user to manipulate the

output register clock inputs quasi independently with the C and

Parameter Synopsis

- 333

tKHKH

tKHQV

3.0 ns

0.45 ns

-300

3.3 ns

0.45 ns

-250

4.0 ns

0.45 ns

-200

5.0 ns

0.45 ns

-167

6.0 ns

0.50 ns

Rev: 1.01a 2/2006

1/29

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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