MC74HC574A
Octal 3-State Noninverting
D Flip-Flop
High−Performance Silicon−Gate CMOS
The MC74HC574A is identical in pinout to the LS574. The device
inputs are compatible with standard CMOS outputs; with pull−up
resistors, they are compatible with LSTTL outputs.
Data meeting the set−up time is clocked to the outputs with the
rising edge of the Clock. The Output Enable input does not affect the
states of the flip−flops but when Output Enable is high, all device
outputs are forced to the high−impedance state. Thus, data may be
stored even when the outputs are not enabled.
The HC574A is identical in function to the HC374A but has the
flip−flop inputs on the opposite side of the package from the outputs to
facilitate PC board layout.
Features
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SOIC−20
DW SUFFIX
CASE 751D
TSSOP−20
DT SUFFIX
CASE 948E
SOEIAJ−20
F SUFFIX
CASE 967
PIN ASSIGNMENT
OUTPUT
ENABLE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
CLOCK
•
•
•
•
•
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
•
Chip Complexity: 266 FETs or 66.5 Equivalent Gates
•
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free and are RoHS Compliant
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
OUTPUT ENABLE
2
3
4
5
6
7
8
9
11
1
PIN 20 = V
CC
PIN 10 = GND
19
18
17
16
15
14
13
12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
NONINVERTING
OUTPUTS
MARKING DIAGRAMS
20
HC574A
AWLYYWWG
20
HC
574A
ALYWG
G
1
TSSOP−20
20
74HC574A
AWLYWWG
1
SOEIAJ−20
1
SOIC−20
A
WL, L
YY, Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
OE
L
L
L
H
Clock
D
H
L
X
X
Output
Q
H
L
No Change
Z
Figure 1. Logic Diagram
L,H,
X
X = Don’t Care
Z = High Impedance
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 15
Publication Order Number:
MC74HC574A/D
MC74HC574A
Design Criteria
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
Speed Power Product
*Equivalent to a two−input NAND gate.
Value
66.5
1.5
5.0
0.0075
Units
ea.
ns
mW
pJ
MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
STG
T
L
T
J
q
JA
P
D
MSL
F
R
V
ESD
DC Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature under Bias
Thermal Resistance
Power Dissipation in Still Air at 85_C
Moisture Sensitivity
Flammability Rating
ESD Withstand Voltage
Oxygen Index: 30% − 35%
Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
Above V
CC
and Below GND at 85_C (Note 5)
SOIC
TSSOP
SOIC
TSSOP
(Note 1)
Parameter
Value
−0.5 to +7.0
−0.5 to V
CC
+ 0.5
−0.5 to V
CC
+ 0.5
±20
±35
±35
±75
±75
−65 to +150
260
+150
96
128
500
450
Level 1
UL 94 V−0 @ 0.125 in
> 4000
> 300
> 1000
±300
V
Unit
V
V
V
mA
mA
mA
mA
mA
_C
_C
_C
_C/W
mW
I
Latchup
Latchup Performance
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. I
O
absolute maximum rating must be observed.
2. Tested to EIA/JESD22−A114−A.
3. Tested to EIA/JESD22−A115−A.
4. Tested to JESD22−C101−A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
, V
O
T
A
t
r
, t
f
DC Supply Voltage
DC Input Voltage, Output Voltage
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 2)
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Parameter
(Referenced to GND)
(Referenced to GND)
Min
2.0
0
−55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
_C
ns
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
6. Unused inputs may not be left open. All inputs must be tied to a high− or low−logic input voltage level.
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2
MC74HC574A
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input
Voltage
Test Conditions
V
out
= V
CC
– 0.1 V
|I
out
|
≤
20
mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4 mA
|I
out
|
≤
6.0 mA
|I
out
|
≤
7.8 mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4 mA
|I
out
|
≤
6.0 mA
|I
out
|
≤
7.8 mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
−55 to 25_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
±0.5
≤
85_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
±5.0
≤
125_C
1.5
2.1
3.15
4.2
0.5
0.9
1.35
1.8
1.9
4.4
5.9
2.2
3.7
5.2
0.1
0.1
0.1
0.4
0.4
0.4
±1.0
±10
mA
mA
Unit
V
V
IL
Maximum Low−Level Input
Voltage
V
out
= 0.1 V
|I
out
|
≤
20
mA
V
V
OH
Minimum High−Level Output
Voltage
Minimum High−Level Output
Voltage
Maximum Low−Level Output
Voltage
V
in
= V
IH
|I
out
|
≤
20
mA
V
in
= V
IH
V
V
OH
V
V
OL
V
in
= V
IL
|I
out
|
≤
20
mA
V
in
= V
IL
V
I
in
I
OZ
Maximum Input Leakage
Current
Maximum Three−State
Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
Output in High−Impedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0
mA
I
CC
6.0
4.0
40
160
mA
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3
MC74HC574A
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF; Input t
r
= t
f
= 6.0 ns)
Symbol
f
max
Parameter
Maximum Clock Frequency (50% Duty Cycle)
(Figures 2 and 5)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
60
2.0
3.0
4.5
6.0
Guaranteed Limit
−55 to 25_C
6.0
15
30
35
160
105
32
27
150
100
30
26
140
90
28
24
60
27
12
10
10
15
≤
85_C
4.8
10
24
28
200
145
40
34
190
125
38
33
175
120
35
30
75
32
15
13
10
15
≤
125_C
4.0
8.0
20
24
240
190
48
41
225
150
45
38
210
140
42
36
90
36
18
15
10
15
Unit
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q
(Figures 2 and 5)
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to Q
(Figures 3 and 6)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, any Output
(Figures 2 and 5)
ns
C
in
C
out
Maximum Input Capacitance
Maximum Three−State Output Capacitance, Output in High−Impedance
State
pF
pF
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Enabled Output)*
24
pF
*Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
.
TIMING REQUIREMENTS
(C
L
= 50 pF; Input t
r
= t
f
= 6.0 ns)
Guaranteed Limit
V
CC
Symbol
t
su
Parameter
Minimum Setup Time, Data to Clock
Figure
4
Volts
2.0
3.0
4.6
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
–55 to 25_C
Min
50
40
10
9.0
5.0
5.0
5.0
5.0
75
60
15
13
1000
800
500
400
Max
≤
85_C
Min
65
50
13
11
5.0
5.0
5.0
5.0
95
80
19
16
1000
800
500
400
Max
≤
125_C
Min
75
60
15
13
5.0
5.0
5.0
5.0
110
90
22
19
1000
800
500
400
Max
Unit
ns
t
h
Minimum Hold Time, Clock to Data
4
ns
t
w
Minimum Pulse Width, Clock
2
ns
t
r
, t
f
Maximum Input Rise and Fall Times
2
ns
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MC74HC574A
SWITCHING WAVEFORMS
t
r
CLOCK
90%
50%
10%
t
w
1/f
max
t
PLH
Q
90%
50%
10%
t
TLH
t
THL
t
PHL
t
f
V
CC
GND
V
M
t
PZH
Q
MC74HC574A: V
M
= V
OH
x 0.5
MC74HCT574A: V
M
= 1.3 V @ V
CC
= 3 V
t
PHZ
10%
90%
OUTPUT
ENABLE
V
CC
V
M
GND
t
PZL
Q
t
PLZ
HIGH
IMPEDANCE
V
OL
V
OH
Figure 2.
Figure 3.
TEST POINT
VALID
V
CC
DATA
50%
GND
t
su
CLOCK
t
h
V
CC
50%
GND
DEVICE
UNDER
TEST
OUTPUT
C
L
*
*Includes all probe and jig capacitance.
Figure 4.
Figure 5.
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
C
Q
D
11
1
19
D0
2
Q0
D1
3
18
Q1
D2
4
17
Q2
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
D3
5
16
Q3
D4
6
15
Q4
C
L
*
D5
*Includes all probe and jig capacitance.
D6
7
14
Q5
8
13
Q6
Figure 6. Test Circuit
D7
9
12
Q7
CLOCK
OUTPUT ENABLE
Figure 7. Expanded Logic Diagram
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