FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer With/Integrated Fanout Buffer
G
ENERAL
D
ESCRIPTION
The 843256 is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout
Buffer designed for Fibre Channel and Gigabit Ethernet applications.
The output frequency can be set using the frequency select pins and
a 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for
SONET. The low phase noise characteristics of the 843256 make it
an ideal clock for these demanding applications.
843256
DATASHEET
F
EATURES
• Six 3.3V differential LVPECL output pairs
• Output frequency range: 62.5MHz to 625MHz
•
Crystal input frequency range: 15.625MHz to 25.5MHz
•
RMS phase jitter at 156.25MHz, using a 25MHz crystal
(1.875MHz to 20MHz): 0.41ps (typical) @ 3.3V
•
Operating supply modes:
Core/Output
3.3V/3.3V
3.3V/2.5V
• 0°C to 70°C ambient operating temperature
•
Available in lead-free (RoHS 6) package
S
ELECT
F
UNCTION
T
ABLE
Inputs
FB_SEL
0
0
0
0
1
1
1
1
N_SEL1
0
0
1
1
0
0
1
1
N_SEL0
0
1
0
1
0
1
0
1
M Divide
25
25
25
25
32
32
32
32
Function
N Divide
1
2
4
5
1
2
4
8
M/N
25
12.5
6.25
5
32
16
8
4
B
LOCK
D
IAGRAM
PLL_BYPASS
Pullup
Q0
nQ0
Q1
P
IN
A
SSIGNMENT
1
XTAL_IN
OSC
XTAL_OUT
PLL
0
N
Output
Divider
nQ1
Q2
nQ2
M
Feedback
Divider
FB_SEL
Pulldown
N_SEL1
N_SEL0
Pullup
Pullup
Q3
nQ3
Q4
nQ4
Q5
nQ5
24-Lead TSSOP, E-Pad
4.40mm x 7.8mm x 0.92mm
body package
G Package
Top View
843256 REVISION B DECEMBER 18, 2014
1
©2014 Integrated Device Technology, Inc.
843256 DATA SHEET
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1, 2
3, 4
5, 6
7, 8
9
10
11
12
13,
14
15,
18
16, 17
19, 20
21, 22
23, 24
Name
V
CCO
nQ2, Q2
nQ1, Q1
nQ0, Q0
PLL_BYPASS
V
CCA
V
CC
FB_SEL
XTAL_IN, XTAL_
OUT
N_SEL0
N_SEL1
V
EE
nQ5, Q5
nQ4, Q4
nQ3, Q3
Output
Output
Output
Power
Output
Output
Output
Input
Power
Power
Input
Input
Input
Pullup
Pulldown
Pullup
Type
Description
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Selects between the PLL and crystal inputs as the input to the dividers.
When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT.
LVCMOS / LVTTL interface levels.
Analog supply pin.
Core supply pin.
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Output frequency select pin. LVCMOS/LVTTL interface levels.
Negative supply pin.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer With/Integrated Fanout Buffer
2
REVISION B 12/18/14
843256 DATA SHEET
T
ABLE
3. C
RYSTAL
F
UNCTION
T
ABLE
Inputs
XTAL (MHz)
20
20
20
20
21.25
24
24
24
24
25
25
25
25
25.5
15.625
18.5625
18.75
18.75
18.75
18.75
19.44
19.44
19.44
19.44
19.53125
19.53125
19.53125
19.53125
20
FB_SEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N_SEL1
0
0
1
1
1
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
N_SEL0
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
1
M
25
25
25
25
25
25
25
25
25
25
25
25
25
25
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
500
500
500
500
531.25
600
600
600
600
625
625
625
625
637.5
500
594
600
600
600
600
622.08
622.08
622.08
622.08
625
625
625
625
640
Function
VCO (MHz)
N
1
2
4
5
5
1
2
4
5
1
2
4
5
4
8
8
1
2
4
8
1
2
4
8
1
2
4
8
8
Output (MHz)
500
250
125
100
106.25
600
300
150
120
625
312.5
156.25
125
159.375
62.5
74.25
600
300
150
75
622.08
311.04
155.52
77.76
625
312.5
156.25
78.125
80
REVISION B 12/18/14
3
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer With/Integrated Fanout Buffer
843256 DATA SHEET
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
Continuous Current
Surge Current
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
37°C/W (0 mps)
-65°C to 150°C
N OT E : S t r e s s e s b eyo n d t h o s e l i s t e d u n d e r A b s o l u t e
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics
or
AC Characteristics
is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V– 0.12
cc
Typical
3.3
3.3
3.3
Maximum
3.465
3.465
3.465
190
12
Units
V
V
V
mA
mA
3.135
T
ABLE
4B. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
CC
V
CCA
V
CCO
I
EE
I
CCA
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Test Conditions
Minimum
3.135
V– 0.12
cc
Typical
3.3
3.3
2.5
Maximum
3.465
3.465
2.625
190
12
Units
V
V
V
mA
mA
2.375
T
ABLE
4C. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
IH
V
IL
I
IH
Parameter
Input High Voltage
Input Low Voltage
FB_SEL
Input High Current
PLL_BYPASS,
N_SEL0, N_SEL1
FB_SEL
I
IL
Input Low Current
PLL_BYPASS,
N_SEL0, N_SEL1
V
CC
= V
IN
= 3.465V
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
-5
-150
Test Conditions
Minimum
2
-0.3
Typical
Maximum
V
CC
+ 0.3
0.8
150
5
Units
V
V
µA
µA
µA
µA
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer With/Integrated Fanout Buffer
4
REVISION B 12/18/14
843256 DATA SHEET
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
Ω
Test Conditions
Minimum
V - 1.4
CCO
Typical
Maximum
V - 0.9
CCO
Units
V
V
V
V - 2.0
CCO
V - 1.7
CCO
0.6
1.0
NOTE 1: Outputs terminated with 50 to V
CCO
- 2V.
T
ABLE
5. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
15.625
Test Conditions
Minimum
Typical Maximum
25.5
50
7
1
Units
MHz
Ω
pF
mW
Fundamental
T
ABLE
6A. AC C
HARACTERISTICS
,
V
CC
= V
CCO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
F
OUT
tjit(Ø)
tsk(o)
t
R
/ t
F
odc
t
LOCK
Parameter
Output Frequency
RMS Phase Jitter (Random)
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
20% to 80%
F
≤
312.5MHz
OUT
Test Conditions
156.25MHz, Integration Range:
1.875MHz - 20MHz
156.25MHz, Integration Range:
12kHz - 20MHz
Minimum
62.5
Typical
Maximum
625
Units
MHz
ps
ps
0.41
0.85
40
200
47
45
650
53
55
20
ps
ps
%
%
ms
F > 312.5MHz
OUT
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
CC
= 3.3V±5%, V
CCO
= 2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
F
OUT
tjit(Ø)
Parameter
Output Frequency
RMS Phase Jitter (Random)
156.25MHz, Integration Range:
1.875MHz - 20MHz
156.25MHz, Integration Range:
12kHz - 20MHz
20% to 80%
200
46
Test Conditions
Minimum
62.5
0.41
0.85
45
650
54
20
Typical
Maximum
625
Units
MHz
ps
ps
ps
ps
%
ms
tsk(o)
t
R
/ t
F
odc
t
LOCK
Output Skew; NOTE 1, 2
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
For NOTES, please see Table 6A above.
REVISION B 12/18/14
5
FemtoClock
®
Crystal-to-3.3V LVPECL
Frequency Synthesizer With/Integrated Fanout Buffer
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