DS28CZ04
4Kb I²C/SMBus EEPROM
with Nonvolatile PIO
www.maxim-ic.com
GENERAL DESCRIPTION
The DS28CZ04 combines 4Kb (512 x 8) EEPROM
with 4 PIO lines. Communication with the device is
accomplished with an industry standard I²C and
SMBus™
interface. The memory is organized as two
segments of 256 bytes with single byte and up to 16-
byte block write capability. Individual PIO lines may
be configured as inputs or outputs. The power-on
state of PIO programmed as outputs is stored in non-
volatile memory. All PIO may be reconfigured by the
user through the serial interface.
FEATURES
4Kb (512 x 8) EEPROM Organized in Two 256-
Byte Blocks
Single Byte and up to 16-Byte EEPROM Write
Sequences
Write-Protect Control Pin for the Entire EEPROM
Array
Endurance 200k Cycles per Block at 25°C; 10ms
max EEPROM Write Cycle
4 PIO Lines
Each PIO is Configured to Input or Output Mode
on Startup by Stored Value
All PIOs are Reconfigurable after Startup
Serial Interface User-Programmable for I²C Bus
and SMBus Compatibility
Supports 100kHz and 400kHz I²C Communica-
tion Speeds
Operating Range: 2.0V to 5.25V, -40°C to +85°C
4mm x 4mm 12-Pin TQFN Package
APPLICATIONS
•
•
•
•
4G SFP Copper Modules
SFF-8472, SFP Fiber Modules
RAID Systems
Servers
TYPICAL OPERATING CIRCUIT
V
CC
T
V
CC
MOD-DEF2
MOD-DEF1
LOS
(from receiver)
ORDERING INFORMATION
PART
DS28CZ04G-4+
DS28CZ04G-4+T
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
TQFN12-EP
*
4x4mm²
TQFN12-EP
*
4x4mm²
Tape-and-Reel
DS28CZ04
SDA
SCL
PIO0
WP
A2
A1 GND
MRZ
PIO3
PIO2
PIO1
V
CC1
V
CC2
MAX3982
PE1
PE0
OUTLEV
IN+
IN-
TX_DISABLE
GND
V
EE
T
LOS
OUT+
OUT-
LOSLEV
EP
Connect to
V
CC
or GND
*EP = Exposed Paddle
+Denotes lead-free package.
PIN CONFIGURATION
GND
SDA
11
12
A1 1
A2 2
PIO3 3
10
9 WP
8 MRZ
7 VCC
4
PIO2
5
PIO1
6
PIO0
SCL
V
EE
T
From SFP
connector
Small Form-factor Pluggable (SFP) Circuit
SMBus is a trademark of Intel Corp.
Thin 12-Lead 4mm × 4mm QFN (Top View)
Package Outline Drawing
21-0139
Package Code T1244+4
Note:
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here:
www.maxim-ic.com/errata.
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REV: 061107
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
Maximum Current SDA, SCL, A2, A1, WP, MRZ Pin
Maximum Current each PIO Pin
Maximum GND and V
CC
Current
Operating Temperature Range
Junction Temperature
Storage Temperature Range
Soldering Temperature
-0.5V, +6V
±20mA
±20mA
100mA
-40°C to +85°C
+150°C
-55°C to +125°C
See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS
(-40°C to +85°C, see Note 1)
PARAMETER
Supply Voltage
Standby Current (Note 2)
Operating Current
Programming Current
Power-up Wait Time
EEPROM
Programming Time
Endurance
Data Retention
PIO Pins, See Figures 8, 9
LOW-Level Output Voltage
HIGH-Level Output Voltage
LOW-Level Input Voltage
HIGH-Level Input Voltage
Output Data Valid Time
PIO Read Setup Time
PIO Read Hold Time
Leakage Current
SYMBOL
V
CC
I
CCS
I
CCA
I
PROG
t
POIP
t
PROG
N
CYCLE
t
RET
V
OL
V
OH
V
IL
V
IH
t
PV
t
PS
t
PH
I
L
(Note 5)
(Note 5)
High Impedance, at
V
CCMAX
CONDITIONS
Bus idle, V
CC
= 5.25V
Bus active at 400kHz,
V
CC
= 5.25V
V
CC
= 5.25V
(Note 3)
MIN
2.0
1.5
250
500
TYP
MAX
5.25
4
500
1000
100
10
UNITS
V
µA
µA
µA
µs
ms
⎯
years
V
V
V
V
µs
ns
ns
µA
V
V
V
At +25°C (Notes 4, 5)
At +85°C (Notes 5, 6)
1mA sink current
500μA source current
200k
40
0
V
CC
-
0.5V
0.4
-0.3
0.7 ×
V
CC
0.3 × V
CC
V
CC
+
0.3V
1
150
150
-1
-0.3
0.7 ×
V
CC
+1
SCL, SDA, A2, A1, WP, MRZ Pins (Note 7), See Figure 6
LOW Level Input Voltage
V
IL
HIGH Level Input Voltage
Hysteresis of Schmitt Trigger
Inputs
LOW Level Output Voltage
Output Fall Time from V
Ihmin
to
V
ILmax
(Notes 5, 10)
Pulse Width of Spikes that are
Suppressed by the Input Filter
V
IH
V
hys
V
OL
t
of
t
SP
(Note 8)
(Notes 5, 9)
At 4mA Sink Current,
open drain
Bus Capacitance from
10pF to 400pF
SDA and SCL pins only
(Note 5)
0.3 × V
CC
V
CCmax
+
0.3V
0.05 ×
V
CC
0.4
20 +
0.1C
B
V
ns
ns
250
50
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DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
PARAMETER
Input Current with an Input
Voltage Between 0.1V
CC
and
0.9V
CCmax
Input Capacitance
SCL Clock Frequency
Bus Time-Out
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
LOW Period of the SCL Clock
(Note 13)
HIGH Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time (Notes 14, 15)
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a
STOP and START Condition
Capacitive Load for Each Bus
Line
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
SYMBOL
I
I
C
I
f
SCL
t
TIMEOUT
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
SU:STO
t
BUF
C
B
CONDITIONS
(Note 11)
(Notes 5, 9)
(Note 12)
(Note 12)
(Note 13)
V
CC
≥
2.7V
V
CC
< 2.7V
(Note 13)
(Note 13)
V
CC
≥
2.7V
V
CC
< 2.7V
(Notes 13, 16)
(Note 13)
(Note 13)
(Notes 5, 13)
MIN
-10
TYP
MAX
10
10
400
75
UNITS
µA
pF
kHz
ms
µs
µs
µs
µs
0.9
1.1
µs
ns
µs
µs
400
pF
25
0.6
1.3
1.5
0.6
0.6
0.3
0.3
100
0.6
1.3
Specifications at -40°C are guaranteed by design and characterization only and not production tested.
To the first order, this current is independent of the supply voltage value.
All PIO are tri-stated at beginning of reset prior to setting to Power-On values.
This specification is valid for each 16-byte memory block.
Not production tested. Guaranteed by design or characterization.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time
storage at elevated temperatures is not recommended; the device can lose its write capability after 10
years at +125°C or 40 years at +85°C.
All values are referenced to V
IHmin
and V
ILmax
levels.
The maximum specification value is guaranteed by design, not production tested.
Applies to SDA and SCL.
C
B
= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I²C-Bus Specification v2.1 are allowed.
The DS28CZ04 does not obstruct the SDA and SCL lines if V
CC
is switched off.
The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL
stays at the same logic level or SDA stays low for this interval, the DS28CZ04 behaves as though it
has sensed a STOP condition.
System Requirement
The DS28CZ04 provides a hold time of at least 300ns for the SDA signal (referred to the V
IHmin
of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
The maximum t
HD:DAT
has only to be met if the device does not stretch the low period (t
LOW
) of the SCL
signal.
A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
t
SU:DAT
≥
250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line t
rmax
+ t
SU:DAT
= 1000 + 250 = 1250ns (according to the
standard-mode I²C-bus specification) before the SCL line is released.
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DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
EP
NAME
A1
A2
PIO3
PIO2
PIO1
PIO0
V
CC
MRZ
WP
SCL
SDA
GND
GND
FUNCTION
Device Address Bit 1
Device Address Bit 2
PIO line #3
PIO line #2
PIO line #1
PIO line #0
Power Supply Input
Master Reset (active-low). Performs a reset of the serial interface and the PIOs without
power-cycling the device.
Write Protect input, to be connected to V
CC
or GND. When connected to V
CC
, the entire
EEPROM array is write-protected. Normal read/write access when connected to GND.
Changing the pin state during a write access will cause unpredictable results.
I²C/SMBus serial clock input; must be tied to V
CC
through a pullup resistor.
I²C/SMBus bidirectional serial data line; must be tied to V
CC
through a pullup resistor.
Ground supply for the device.
Exposed Paddle. Solder evenly to the board’s ground plane for proper operation. See
Application Note 3273
for additional information.
OVERVIEW
The DS28CZ04 consists of a serial I²C/SMBus interface, 4Kb of EEPROM and four bidirectional PIO channels, as
shown in the block diagram in Figure 1. The device communicates with a host processor through its I²C interface in
standard-mode or in fast-mode; the user can switch the interface from I²C bus to SMBus mode. Two address pins
allow 4 DS28CZ04 to reside on the same bus segment. A Master reset pin permits a full device reset without power
cycling.
The device has a memory range of 512 bytes, organized as two segments (lower half, upper half) of 256 bytes
(Figure 2). The memory map and device addressing is compatible with SFF-8472 Digital Diagnostic address
assignments. The entire EEPROM can be write-protected by tying the WP pin to V
CC
. The PIO pins can be
accessed through one address (= single-address mode) or through separate addresses (= multi-address mode).
PIO direct access addressing allows fast generation of data patterns and fast sampling.
The DS28CZ04 includes several EEPROM registers for the user to select whether the device powers up in SFF
mode and to define the power-on default conditions for individual PIO output state (high, low, in output mode),
individual PIO data direction (in, out), individual PIO output type (push-pull, open drain), individual PIO read bit
inversion (true, false). Once powered up, the PIO settings can be overwritten through SRAM registers without
affecting the power-on defaults.
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DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
Figure 1. Block Diagram
SCL
SDA
A2
A1
MRZ
WP
Serial
Interface
Control
Power
Distribu-
tion
V
CC
GND
4-Kbit
EEPROM
PIO
Control
PIO3
PIO2
PIO1
PIO0
Figure 2A. Memory Map (Device Address = A0h)
ADDRESS
00h to 74h
75h
76h
77h
78h to 79h
7Ah
7Bh
7Ch to 7Fh
80h to FFh
TYPE
EEPROM
EEPROM
EEPROM
EEPROM
⎯
SRAM
SRAM
SRAM
EEPROM
ACCESS
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
User memory
Special function/user memory; controls whether
device powers-up into SFF Mode
Power-on default for PIO output state and
direction for all PIOs
Power-on default for PIO output type and read-
inversion for all PIOs
Reserved (reads FFh)
Direction setting for all PIOs and device
control/status register
PIO read-inversion and PIO output type for all
PIOs
PIO Read/Write Access Registers
User memory
DESCRIPTION
Figure 2B. Memory Map (Device Address = A2h)
ADDRESS
00h to 6Dh
6Eh
6Fh to EFh
F0h to FFh
TYPE
EEPROM
EEPROM
⎯
EEPROM
⎯
ACCESS
R/W
R/W
R
R/W
R
User memory
SFF Mode off: User memory
SFF Mode on: SFF Optional Status Register
User memory
Reserved (reads FFh)
DESCRIPTION
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