19-5856; Rev 4; 5/11
DS26514
4-Port T1/E1/J1 Transceiver
______________ General Description
The DS26514 is a 4-port framer and line interface
unit (LIU) combination for T1, E1, J1 applications.
Each port is independently configurable, supporting
both long-haul and short-haul lines. The DS26514
single-chip transceiver (SCT) is software and pinout
compatible with the 8-port DS26518. It is nearly
software compatible with the DS26528 and its
derivatives.
_______________________ Features
♦
♦
♦
♦
Four Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer)
Independent T1, E1, or J1 Selections for Each
Transceiver
Fully Internal Impedance Match, No External
Resistor
Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Twisted Pair,
110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
and 75Ω E1 Coaxial Applications
Hitless Protection Switching
Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411
External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode
Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments
Transmit Open- and Short-Circuit Detection
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231
Transmit Synchronizer
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port
Alarm Detection and Insertion
T1 Framing Formats of D4, SLC-96, and ESF
J1 Support
E1 G.704 and CRC-4 Multiframe
T1-to-E1 Conversion
___________________ Applications
Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
♦
♦
______________ Functional Diagram
DS26514
T1/E1/J1
NETWORK
♦
♦
T1/J1/E1
Transceiver
x4
BACKPLANE
TDM
♦
♦
♦
♦
______________ Ordering Information
PART
DS26514GN
DS26514GN+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
256 TE-CSBGA
256 TE-CSBGA
♦
♦
♦
♦
♦
+Denotes a lead(Pb)-free/RoHS compliant package.
Features continued in Section
2.
Maxim Integrated Products 1
Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
revisions of any device may be simultaneously available through various sales channels. For information about device
errata, go to:
www.maxim-ic.com/errata.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
DS26514 4-Port T1/E1/J1 Transceiver
TABLE OF CONTENTS
1.
2.
DETAILED DESCRIPTION ................................................................................................. 9
FEATURE HIGHLIGHTS .................................................................................................. 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
G
ENERAL
................................................................................................................................... 10
L
INE
I
NTERFACE
......................................................................................................................... 10
C
LOCK
S
YNTHESIZERS
............................................................................................................... 10
J
ITTER
A
TTENUATOR
.................................................................................................................. 10
F
RAMER
/F
ORMATTER
................................................................................................................. 11
S
YSTEM
I
NTERFACE
................................................................................................................... 11
HDLC C
ONTROLLERS
................................................................................................................. 12
T
EST AND
D
IAGNOSTICS
............................................................................................................. 12
M
ICROCONTROLLER
P
ARALLEL
P
ORT
.......................................................................................... 12
S
LAVE
S
ERIAL
P
ERIPHERAL
I
NTERFACE
(SPI) F
EATURES
.......................................................... 12
3.
4.
5.
6.
7.
8.
8.1
APPLICATIONS ............................................................................................................... 13
SPECIFICATIONS COMPLIANCE ................................................................................... 14
ACRONYMS AND GLOSSARY ....................................................................................... 16
MAJOR OPERATING MODES ......................................................................................... 17
BLOCK DIAGRAMS ......................................................................................................... 18
PIN DESCRIPTIONS ........................................................................................................ 20
P
IN
F
UNCTIONAL
D
ESCRIPTION
................................................................................................... 20
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
FUNCTIONAL DESCRIPTION ......................................................................................... 28
P
ROCESSOR
I
NTERFACE
............................................................................................................. 28
SPI Serial Port Mode....................................................................................................................... 28
SPI Functional Timing Diagrams ..................................................................................................... 28
Backplane Clock Generation ........................................................................................................... 31
CLKO Output Clock Generation ...................................................................................................... 32
9.1.1
9.1.2
9.2.1
9.2.2
C
LOCK
S
TRUCTURE
.................................................................................................................... 31
R
ESETS AND
P
OWER
-D
OWN
M
ODES
........................................................................................... 33
I
NITIALIZATION AND
C
ONFIGURATION
........................................................................................... 34
Example Device Initialization and Sequence ................................................................................... 34
9.4.1
G
LOBAL
R
ESOURCES
.................................................................................................................. 34
P
ER
-P
ORT
R
ESOURCES
.............................................................................................................. 34
D
EVICE
I
NTERRUPTS
.................................................................................................................. 34
S
YSTEM
B
ACKPLANE
I
NTERFACE
................................................................................................. 36
Elastic Stores.................................................................................................................................. 36
IBO Multiplexing .............................................................................................................................. 39
H.100 (CT Bus) Compatibility .......................................................................................................... 45
Transmit and Receive Channel Blocking Registers.......................................................................... 47
Transmit Fractional Support (Gapped Clock Mode) ......................................................................... 47
Receive Fractional Support (Gapped Clock Mode) .......................................................................... 47
T1 Framing ..................................................................................................................................... 48
E1 Framing ..................................................................................................................................... 51
T1 Transmit Synchronizer ............................................................................................................... 53
Signaling ......................................................................................................................................... 54
T1 Data Link ................................................................................................................................... 59
E1 Data Link ................................................................................................................................... 61
Maintenance and Alarms................................................................................................................. 62
2 of 305
9.8.1
9.8.2
9.8.3
9.8.4
9.8.5
9.8.6
9.9
F
RAMERS
................................................................................................................................... 48
9.9.1
9.9.2
9.9.3
9.9.4
9.9.5
9.9.6
9.9.7
19-5856; Rev 4; 5/11
DS26514 4-Port T1/E1/J1 Transceiver
9.9.8
9.9.9
9.9.10
9.9.11
9.9.12
9.9.13
9.9.14
9.9.15
9.9.16
9.9.17
Alarms ............................................................................................................................................ 65
Error Count Registers ..................................................................................................................... 67
DS0 Monitoring Function ................................................................................................................. 69
Transmit Per-Channel Idle Code Generation ................................................................................... 70
Receive Per-Channel Idle Code Insertion ........................................................................................ 70
Per-Channel Loopback ................................................................................................................... 70
E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only) ................................................................ 70
T1 Programmable In-Band Loop Code Generator............................................................................ 71
T1 Programmable In-Band Loop Code Detection ............................................................................ 72
Framer Payload Loopbacks............................................................................................................. 73
9.10
9.10.1
9.10.2
9.10.3
HDLC C
ONTROLLERS
............................................................................................................. 74
HDLC-64 Controller ........................................................................................................................ 74
Transmit HDLC-64 Controller .......................................................................................................... 77
HDLC-256 Controller....................................................................................................................... 78
9.11
9.12
9.12.1
9.12.2
9.12.3
9.12.4
9.12.5
9.12.6
P
OWER
-S
UPPLY
D
ECOUPLING
................................................................................................. 84
L
INE
I
NTERFACE
U
NITS
(LIU
S
) ................................................................................................. 85
LIU Operation ................................................................................................................................. 87
Transmitter ..................................................................................................................................... 88
Receiver ......................................................................................................................................... 91
Hitless Protection Switching (HPS).................................................................................................. 95
Jitter Attenuator .............................................................................................................................. 96
LIU Loopbacks ................................................................................................................................ 97
9.13
9.13.1
9.13.2
B
IT
E
RROR
-R
ATE
T
EST
F
UNCTION
(BERT) ..............................................................................100
BERT Repetitive Pattern Set ......................................................................................................... 101
BERT Error Counter...................................................................................................................... 101
10.
DEVICE REGISTERS ..................................................................................................... 102
R
EGISTER
L
ISTINGS
...............................................................................................................102
Global Register List ....................................................................................................................... 103
Framer Register List...................................................................................................................... 104
LIU Register List ........................................................................................................................... 111
BERT Register List ....................................................................................................................... 112
HDLC-256 Register List ................................................................................................................ 113
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
10.1
10.2
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
R
EGISTER
B
IT
M
APS
..............................................................................................................114
Global Register Bit Map ................................................................................................................ 114
Framer Register Bit Map ............................................................................................................... 115
LIU Register Bit Map ..................................................................................................................... 124
BERT Register Bit Map ................................................................................................................. 125
HDLC-256 Register Bit Map .......................................................................................................... 126
10.3
10.4
10.4.1
10.4.2
G
LOBAL
R
EGISTER
D
EFINITIONS
.............................................................................................127
F
RAMER
R
EGISTER
D
ESCRIPTIONS
.........................................................................................142
Receive Register Descriptions ...................................................................................................... 142
Transmit Register Descriptions ..................................................................................................... 199
10.5
10.6
10.7
10.8
10.8.1
10.8.2
LIU R
EGISTER
D
EFINITIONS
....................................................................................................236
BERT R
EGISTER
D
EFINITIONS
................................................................................................246
E
XTENDED
BERT R
EGISTER
D
EFINITIONS
...............................................................................253
HDLC-256 R
EGISTER
D
EFINITIONS
.........................................................................................257
Transmit HDLC-256 Register Definitions ....................................................................................... 257
Receive HDLC-256 Register Definitions ........................................................................................ 260
11.
FUNCTIONAL TIMING ................................................................................................... 264
T1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
.........................................................................264
T1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
....................................................................269
E1 R
ECEIVER
F
UNCTIONAL
T
IMING
D
IAGRAMS
.........................................................................274
E1 T
RANSMITTER
F
UNCTIONAL
T
IMING
D
IAGRAMS
...................................................................278
11.1
11.2
11.3
11.4
12.
OPERATING PARAMETERS ......................................................................................... 283
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19-5856; Rev 4; 5/11
DS26514 4-Port T1/E1/J1 Transceiver
12.1
12.2
T
HERMAL
C
HARACTERISTICS
..................................................................................................284
L
INE
I
NTERFACE
C
HARACTERISTICS
........................................................................................284
M
ICROPROCESSOR
B
US
AC C
HARACTERISTICS
.......................................................................285
SPI Bus Mode ............................................................................................................................... 285
13.
AC TIMING CHARACTERISTICS .................................................................................. 285
13.1.1
13.1
13.2
JTAG I
NTERFACE
T
IMING
.......................................................................................................296
TAP C
ONTROLLER
S
TATE
M
ACHINE
........................................................................................298
Test-Logic-Reset........................................................................................................................... 298
Run-Test-Idle ................................................................................................................................ 298
Select-DR-Scan ............................................................................................................................ 298
Capture-DR .................................................................................................................................. 298
Shift-DR ........................................................................................................................................ 298
Exit1-DR ....................................................................................................................................... 298
Pause-DR ..................................................................................................................................... 298
Exit2-DR ....................................................................................................................................... 298
Update-DR.................................................................................................................................... 298
Select-IR-Scan .......................................................................................................................... 298
Capture-IR ................................................................................................................................ 299
Shift-IR ...................................................................................................................................... 299
Exit1-IR ..................................................................................................................................... 299
Pause-IR ................................................................................................................................... 299
Exit2-IR ..................................................................................................................................... 299
Update-IR .................................................................................................................................. 299
SAMPLE:PRELOAD ..................................................................................................................... 301
BYPASS ....................................................................................................................................... 301
EXTEST ....................................................................................................................................... 301
CLAMP ......................................................................................................................................... 301
HIGHZ .......................................................................................................................................... 301
IDCODE ....................................................................................................................................... 301
14.
JTAG BOUNDARY SCAN AND TEST ACCESS PORT ................................................ 297
14.1.1
14.1.2
14.1.3
14.1.4
14.1.5
14.1.6
14.1.7
14.1.8
14.1.9
14.1.10
14.1.11
14.1.12
14.1.13
14.1.14
14.1.15
14.1.16
14.1
14.2
14.2.1
14.2.2
14.2.3
14.2.4
14.2.5
14.2.6
I
NSTRUCTION
R
EGISTER
.........................................................................................................301
14.3
14.4
14.4.1
14.4.2
14.4.3
JTAG ID C
ODES
....................................................................................................................302
T
EST
R
EGISTERS
...................................................................................................................302
Boundary Scan Register ............................................................................................................... 302
Bypass Register............................................................................................................................ 302
Identification Register.................................................................................................................... 302
15.
16.
17.
PIN CONFIGURATION ................................................................................................... 303
P
IN
C
ONFIGURATION
—256-B
ALL
TE-CSBGA .........................................................................303
15.1
PACKAGE INFORMATION ............................................................................................ 304
DOCUMENT REVISION HISTORY ................................................................................ 305
19-5856; Rev 4; 5/11
4 of 305
DS26514 4-Port T1/E1/J1 Transceiver
LIST OF FIGURES
Figure 7-1. Block Diagram ................................................................................................................................... 18
Figure 7-2. Detailed Block Diagram ...................................................................................................................... 19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0 ............................................. 29
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0 ............................................. 29
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1 ............................................. 29
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1 ............................................. 29
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0.............................................. 29
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0.............................................. 30
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1.............................................. 30
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1.............................................. 30
Figure 9-9. Backplane Clock Generation .............................................................................................................. 31
Figure 9-10. Device Interrupt Information Flow Diagram ....................................................................................... 35
Figure 9-11. IBO Multiplexer Equivalent Circuit—4.096MHz ................................................................................. 40
Figure 9-12. IBO Multiplexer Equivalent Circuit—8.192MHz ................................................................................. 41
Figure 9-13. IBO Multiplexer Equivalent Circuit—16.384MHz ............................................................................... 42
Figure 9-14. RSYNCn Input in H.100 (CT Bus) Mode ........................................................................................... 46
Figure 9-15. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode................................................................. 46
Figure 9-16. CRC-4 Recalculate Method .............................................................................................................. 70
Figure 9-17. HDLC Message Receive Example.................................................................................................... 76
Figure 9-18. HDLC Message Transmit Example................................................................................................... 78
Figure 9-19. Receive HDLC Example................................................................................................................... 81
Figure 9-20. HDLC Message Transmit Example................................................................................................... 83
Figure 9-21. Network Connection—Longitudinal Protection .................................................................................. 86
Figure 9-22. T1/J1 Transmit Pulse Templates ...................................................................................................... 89
Figure 9-23. E1 Transmit Pulse Templates........................................................................................................... 89
Figure 9-24. Receive LIU Termination Options ..................................................................................................... 91
Figure 9-25. Typical Monitor Application............................................................................................................... 93
Figure 9-26. HPS Block Diagram ......................................................................................................................... 95
Figure 9-27. Jitter Attenuation .............................................................................................................................. 96
Figure 9-28. Loopback Diagram ........................................................................................................................... 97
Figure 9-29. Analog Loopback ............................................................................................................................. 97
Figure 9-30. Local Loopback ................................................................................................................................ 98
Figure 9-31. Remote Loopback 2 ......................................................................................................................... 98
Figure 9-32. Dual Loopback ................................................................................................................................. 99
Figure 11-1. T1 Receive-Side D4 Timing............................................................................................................ 264
Figure 11-2. T1 Receive-Side ESF Timing ......................................................................................................... 264
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled) ............................................................ 265
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ............................................ 265
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ............................................ 266
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode ............................................................... 267
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode ............................................................ 268
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit ................................................................. 268
Figure 11-9. T1 Transmit-Side D4 Timing........................................................................................................... 269
Figure 11-10. T1 Transmit-Side ESF Timing ...................................................................................................... 269
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled) ......................................................... 270
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled) ......................................... 270
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled) ......................................... 271
Figure 11-14. T1 Transmit-Side Interleave Bus Operation—BYTE Mode ............................................................ 272
Figure 11-15. T1 Transmit-Side Interleave Bus Operation—FRAME Mode ......................................................... 273
19-5856; Rev 4; 5/11
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Embedded System
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