MC14569B
Programmable Divide-By-N
Dual 4-Bit Binary/BCD
Down Counter
The MC14569B is a programmable divide−by−N dual 4−bit binary
or BCD down counter constructed with MOS P−Channel and
N−Channel enhancement mode devices (complementary MOS) in
a monolithic structure.
This device has been designed for use with the MC14568B phase
comparator/counter in frequency synthesizers, phase−locked loops,
and other frequency division applications requiring low power
dissipation and/or high noise immunity.
Features
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SOIC−16 WB
DW SUFFIX
CASE 751G
•
Speed−up Circuitry for Zero Detection
•
Each 4−Bit Counter Can Divide Independently in BCD or Binary Mode
•
Can be Cascaded With MC14526B for Frequency Synthesizer
•
•
•
•
Applications
All Outputs are Buffered
Schmitt Triggered Clock Conditioning
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
This Device is Pb−Free and is RoHS Compliant
PIN ASSIGNMENT
ZERO
DETECT
CTL1
P0
P1
P2
P3
CASCADE
FEEDBACK
V
SS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
Q
P7
P6
P5
P4
CTL
2
CLOCK
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation, per Package
(Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
A
WL
YY
WW
G
16
14569B
AWLYYWWG
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
MARKING DIAGRAM
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Package: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
July, 2014 − Rev. 8
Publication Order Number:
MC14569B/D
MC14569B
BLOCK DIAGRAM
P0 P1 P2 P3
CTL = Low for Binary Count
CTL = High for BCD Count
3
4
5
6
CTL
1
CTL
2
2
10
P4 P5 P6 P7
11 12 13
14
V
DD
= PIN 16
V
SS
= PIN 8
15
CLOCK
9
BINARY/BCD
COUNTER #1
CLOCK
LOAD
BINARY/BCD
COUNTER #2
Q
CASCADE 7
FEEDBACK
ZERO DETECT ENCODER
1 ZERO
DETECT
ORDERING INFORMATION
Device
MC14569BDWG
MC14569BDWR2G
NLV14569BDWR2G*
Package
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
SOIC−16 WB
(Pb−Free)
Shipping
†
47 Units / Rail
1000 Units / Tape & Reel
1000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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2
MC14569B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
– 55_C
Characteristic
Output Voltage
V
in
= V
DD
or 0
V
in
= 0 or V
DD
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
“1” Level
V
IH
5.0
10
15
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
−
5.0
10
20
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
2.25
4.50
6.75
2.75
5.50
8.25
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.005
0.010
0.015
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±0.1
7.5
5.0
10
20
125_C
Min
−
−
−
4.95
9.95
14.95
−
−
−
3.5
7.0
11
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
Max
0.05
0.05
0.05
−
−
−
1.5
3.0
4.0
−
−
−
−
−
−
−
−
−
−
±1.0
−
150
300
600
mAdc
Vdc
Unit
Vdc
“1” Level
V
OH
Vdc
Input Voltage
(V
O
= 4.5 or 0.5 Vdc)
(V
O
= 9.0 or 1.0 Vdc)
(V
O
= 13.5 or 1.5 Vdc)
(V
O
= 0.5 or 4.5 Vdc)
(V
O
= 1.0 or 9.0 Vdc)
(V
O
= 1.5 or 13.5 Vdc)
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
“0” Level
V
IL
Vdc
I
OH
Source
mAdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
I
T
I
T
= (0.58
mA/kHz)
f + I
DD
I
T
= (1.20
mA/kHz)
f + I
DD
I
T
= (1.95
mA/kHz)
f + I
DD
mAdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.001.
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3
MC14569B
SWITCHING CHARACTERISTICS
(C
L
= 50 pF, T
A
= 25_C)
All Types
Characteristic
Output Rise Time
Symbol
t
TLH
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
t
PHL
5.0
10
15
5.0
10
15
t
WH
5.0
10
15
5.0
10
15
5.0
10
15
−
−
−
−
−
−
300
150
115
−
−
−
380
150
100
530
225
155
100
45
30
3.5
9.5
13.0
NO LIMIT
600
300
200
1000
400
300
−
−
−
2.1
5.1
7.8
ns
Min
−
−
−
−
−
−
−
−
−
−
−
−
Typ
(Note 5)
100
50
40
100
50
40
420
175
125
675
285
200
Max
200
100
80
200
100
80
700
300
250
1200
500
400
ns
Unit
ns
Output Fall Time
t
THL
ns
Turn−On Delay Time
Zero Detect Output
t
PLH
ns
Q Output
Turn−Off Delay Time
Zero Detect Output
ns
Q Output
Clock Pulse Width
ns
Clock Pulse Frequency
f
cl
MHz
Clock Pulse Rise and Fall Time
t
TLH
, t
THL
ms
5. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
SWITCHING WAVEFORMS
20 ns
20 ns
CLOCK 10%
90%
50%
t
WH
t
PLH
Q
10%
90%
50%
t
TLH
t
THL
t
PHL
ZERO DETECT
t
TLH
f
in
= f
max
20 ns
CLOCK 10%
90%
50%
t
WH
t
PLH
20 ns
t
PHL
90%
10%
t
THL
Figure 1.
Figure 2.
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4
MC14569B
PIN DESCRIPTIONS
INPUTS
CONTROLS
P0, P1, P2, P3 (Pins 3, 4, 5, 6)
− Preset Inputs.
Programmable inputs for the least significant counter. May
be binary or BCD depending on the control input.
P4, P5, P6, P7 (Pins 11, 12, 13, 14)
− Preset Inputs.
Programmable inputs for the most significant counter. May
be binary or BCD depending on the control input.
Clock (Pin 9)
− Preset data is decremented by one on each
positive transition of this signal.
OUTPUTS
Zero Detect (Pin 1)
− This output is normally low and
goes high for one clock cycle when the counter has
decremented to zero.
Q (Pin 15)
− Output of the last stage of the most significant
counter. This output will be inactive unless the preset input
P7 has been set high.
Cascade Feedback (Pin 7)
− This pin is normally set
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
CTL
1
(Pin 2)
− This pin controls the counting mode of the
least significant counter. When set high, counting mode is
BCD. When set low, counting mode is binary.
CTL
2
(Pin 10)
− This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
SUPPLY PINS
V
SS
(Pin 18)
− Negative Supply Voltage. This pin is
usually connected to ground.
V
DD
(Pin 16)
− Positive Supply Voltage. This pin is
connected to a positive supply voltage ranging from 3.0 V
to 18 V.
OPERATING CHARACTERISTICS
The MC14569B is a programmable divide−by−N dual
4−bit down counter. This counter may be programmed (i.e.,
preset) in BCD or binary code through inputs P0 to P7. For
each counter, the counting sequence may be chosen
independently by applying a high (for BCD count) or a low
(for binary count) to the control inputs CTL
1
and CTL
2
.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a
division ratio of one is not possible. After N clock cycles,
one pulse appears on the Zero Detect output. (See Timing
Diagram.) The Q output is the output of the last stage of the
most significant counter (See Tables 1 through 5, Mode
Controls.)
When cascading the MC14569B to the MC14526B, the
Cascade Feedback input, Q, and Zero Detect outputs must
be respectively connected to “0”, Clock, and Load of the
following counter. If the MC14569B is used alone, Cascade
Feedback must be connected to V
DD
.
18
16
f, FREQUENCY (MHz), TYPICAL
14
12
10
8.0
6.0
4.0
2.0
0
- 40
- 20
0
+ 20
+ 40
+ 60
T
A
, AMBIENT TEMPERATURE (°C)
+ 80
+ 100
5.0 V
10 V
V
DD
= 15 V
C
L
= 50 pF
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Embedded System
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