Changes to Ordering Guide .......................................................... 22
5/99—Rev. 0 to Rev. A
Rev. B | Page 2 of 24
AD7863
SPECIFICATIONS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
SAMPLE AND HOLD
−3 dB Small Signal Bandwidth
Aperture Delay
2
Aperture Jitter
2
Aperture Delay Matching
2
DYNAMIC PERFORMANCE
3
Signal-to-(Noise + Distortion) Ratio
4
@ 25°C
T
MIN
to T
MAX
Total Harmonic Distortion
4
Peak Harmonic or Spurious Noise
4
Intermodulation Distortion
4
Second Order Terms
Third Order Terms
Channel-to-Channel Isolation
4
DC ACCURACY
Resolution
Minimum Resolution for Which No
Missing Codes are Guaranteed
Relative Accuracy
4
Differential Nonlinearity
4
AD7863-10, AD7863-3
Positive Gain Error
4
Positive Gain Error Match
4
Negative Gain Error
4
Negative Gain Error Match
4
Bipolar Zero Error
Bipolar Zero Error Match
AD7863-2
Positive Gain Error
4
Positive Gain Error Match
4
Unipolar Offset Error
Unipolar Offset Error Match
ANALOG INPUTS
AD7863-10
Input Voltage Range
Input Resistance
AD7863-3
Input Voltage Range
Input Resistance
AD7863-2
Input Voltage Range
Input Current
A Version
1
7
35
50
350
B Version
1
7
35
50
350
Unit
MHz typ
ns max
ps typ
ps max
f
IN
= 80.0 kHz, f
S
= 175 kSPS
78
77
−82
−82
−93
−89
−86
14
14
±2.5
+2 to −1
±10
10
±10
10
±10
8
±14
16
±14
10
78
77
−82
−82
−93
−89
−86
14
14
±2
+2 to −1
±8
10
±8
10
±8
6
dB min
dB min
dB max
dB max
dB typ
dB typ
dB typ
Bits
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
Test Conditions/Comments
−87 dB typ
−90 dB typ
fa = 49 kHz, fb = 50 kHz
f
IN
= 50 kHz sine wave
Any channel
±10
9
±2.5
3
2.5
100
±10
9
±2.5
3
2.5
100
V
kΩ typ
V
kΩ typ
V
nA max
Rev. B | Page 3 of 24
AD7863
Parameter
REFERENCE INPUT/OUTPUT
REF IN Input Voltage Range
REF IN Input Current
REF OUT Output Voltage
REF OUT Error @ 25°C
REF OUT Error T
MIN
to T
MAX
REF OUT Temperature Coefficient
LOGIC INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
IN
Input Capacitance, C
IN 5
LOGIC OUTPUTS
Output High Voltage, V
OH
Output Low Voltage, V
OL
DB11 to DB0
Floating-State Leakage Current
Floating-State Capacitance
5
Output Coding
AD7863-10, AD7863-3
AD7863-2
CONVERSION RATE
Conversion Time
Mode 1 Operation
Mode 2 Operation
6
Track/Hold Acquisition Time
4, 7
POWER REQUIREMENTS
V
DD
I
DD
Normal Mode (Mode 1)
AD7863-10
AD7863-3
AD7863-2
Power-Down Mode (Mode 2)
I
DD
@ 25°C
8
Power Dissipation
Normal Mode (Mode 1)
AD7863-10
AD7863-3
AD7863-2
Power-Down Mode @ 25°C
1
2
A Version
1
2.375 to 2.625
±100
2.5
±10
±20
25
2.4
0.8
±10
10
4.0
0.4
±10
10
B Version
1
2.375 to 2.625
±100
2.5
±10
±20
25
2.4
0.8
±10
10
4.0
0.4
±10
10
Unit
V
μA max
V nom
mV max
mV max
ppm/°C typ
V min
V max
μA max
pF max
V min
V max
μA max
pF max
Test Conditions/Comments
2.5 V ± 5%
V
DD
= 5 V ± 5%
V
DD
= 5 V ± 5%
I
SOURCE
= 200 μA
I
SINK
= 1.6 mA
Twos complement
Straight (natural) binary
5.2
10.0
0.5
5
5.2
10.0
0.5
5
μs max
μs max
μs max
V nom
For both channels
For both channels
±5% for specified performance
18
16
11
20
18
16
11
20
mA max
mA max
mA max
μA max
40 nA typ. Logic inputs = 0 V or V
DD
94.50
84
57.75
105
94.50
84
57.75
105
mW max
mW max
mW max
μW max
V
DD
= 5.25 V, 70 mW typ
V
DD
= 5.25 V, 70 mW typ
V
DD
= 5.25 V, 45 mW typ
210 nW typ, V
DD
= 5.25 V
Temperature ranges are as follows: A Version and B Version, −40°C to +85°C.
Sample tested during initial release.
3
Applies to Mode 1 operation. See Operating Modes section.
4
See Terminology section.
5
Sample tested @ 25°C to ensure compliance.
6
This 10 μs includes the wake-up time from standby. This wake-up time is timed from the rising edge of CONVST, whereas conversion is timed from the falling edge of
CONVST, for a narrow CONVST pulse width the conversion time is effectively the wake-up time plus conversion time, 10 μs. This can be seen from Figure 6. Note that if
the CONVST pulse width is greater than 5.2 μs, the effective conversion time increases beyond 10 μs.
7
Performance measured through full channel (multiplexer, SHA, and ADC).
8
For best dynamic performance of the AD7863, ATE device testing has to be performed with power supply decoupling in place. In the AD7863 power-down mode of
operation, the leakage current associated with these decoupling capacitors is greater than that of the AD7863 supply current. Therefore, the 40 nA typical figure
shown is characterized and guaranteed by design figure, which reflects the supply current of the AD7863 without decoupling in place. The maximum figure shown in
the Conditions/Comments column reflects the AD7863 with supply decoupling in place—0.1 μF in parallel with 10 μF disc ceramic capacitors on the V
DD
pin and
2 × 0.1 μF disc ceramic capacitors on the V
REF
pin, in both cases to the AGND plane.
Rev. B | Page 4 of 24
AD7863
TIMING CHARACTERISTICS
V
DD
= 5 V ± 5%, AGND = DGND = 0 V, REF = Internal. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
1, 2
t
CONV
t
ACQ
Parallel Interface
t
1
t
2
t
3
t
4
t
5 3
t
6 4
t
7
t
8
1
2
A, B Versions
5.2
0.5
0
0
35
45
30
5
30
10
400
Unit
μs max
μs max
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
Test Conditions/Comments
Conversion time
Acquisition time
CS to RD setup time
CS to RD hold time
CONVST pulse width
RD pulse width
Data access time after falling edge of RD
Bus relinquish time after rising edge of RD
Time between consecutive reads
Quiet time
Sample tested at 25°C to ensure compliance. All input signals are measured with tr = tf = 1 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
See Figure 2.
3
Measured with the load circuit of Figure 3 and defined as the time required for an output to cross 0.8 V or 2.0 V.
4
These times are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
t
ACQ
t
8
CONVST
t
3
BUSY
t
CONV
= 5.2µs
A0
CS
t
1
t
4
RD
t
2
t
7
t
5
DATA
V
A1
V
A2
t
6
V
B1
V
B2
06411-002
Figure 2. Timing Diagram
1.6mA
TO OUTPUT
PIN
50pF
200µA
06411-003
Figure 3. Load Circuit for Access Time and Bus Relinquish Time
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