DS2423P datasheet, PDF - EEWORLD Datasheet

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DS2423P: DescriptionSRAM; Categorystorage storage; File Size675KB，26 Pages; ManufacturerMaxim; Websitehttps://www.maximintegrated.com/en.html

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DS2423P Overview

SRAM

DS2423P Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Maxim
Parts packaging code	SOIC
package instruction	3.70 X 4 MM, 1.50 MM HEIGHT, TSOC-6
Contacts	6
Reach Compliance Code	not_compliant
Maximum access time	15000 ns
Other features	ALSO CONTAINS 64 BIT LASERED ROM
I/O type	COMMON
JESD-30 code	R-PDSO-C6
JESD-609 code	e0
length	3.94 mm
memory density	4096 bit
Memory IC Type	MEMORY CIRCUIT
memory width	1
Humidity sensitivity level	1
Number of functions	1
Number of ports	1, (1 LINE)
Number of terminals	6
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4KX1
Output characteristics	OPEN-DRAIN
Package body material	PLASTIC/EPOXY
encapsulated code	SOC
Encapsulate equivalent code	SOC6,.17
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	240
power supply	3/5 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage (Vsup)	6 V
Minimum supply voltage (Vsup)	2.8 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	MOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	C BEND
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	20
width	3.76 mm

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EVALUATION KIT AVAILABLE

AVAILAB

4kbit 1-Wire

RAM with Counter

FEATURES

DS2423

4096 bits of SRAM

Four 32-bit, read-only counters

Active-low external trigger inputs for two of

the counters with on-chip debouncing

compatible with reed and Wiegand switches

Unique, factory-lasered and tested 64-bit

registration number (8-bit family code + 48-

bit serial number + 8-bit CRC tester) assures

absolute traceability because no two parts are

alike

Memory partitioned into 16 256-bit pages in

for packetizing data

256-bit scratchpad with strict read/write

protocols ensures integrity of data transfer

On-chip 16-bit CRC generator for

safeguarding data transfers

Built-in multidrop controller ensures

compatibility with other MicroLAN products

Directly connects to a single port pin of a

microprocessor and communicates at up to

16.3kbits per second

Overdrive mode boosts communication speed

Functional Diagrams

to 142kbits per second

8-bit family code specifies device

communication requirements to reader

Presence detector acknowledges when reader

first applies voltage

TSOC PACKAGE

PIN DESCRIPTION

Pin 1

Pin 2

Pin 3

Pin 4

Pin 5

Pin 6

ORDERING INFORMATION

DS2423P

DS2423P/T&R

DS2423P+

TOP VIEW

3.7mm x 4.0mm x 1.5mm

SIDE VIEW

+ Indicates lead-free compliance.

The DS2423 1-Wire

RAM with Counters is a fully static, read/write memory for battery operation in a

low-cost, six-lead TSOC, surface-mount package. The memory is organized as 16 pages of 256 bits each.

In addition, the device has four counters, two of them with external trigger inputs called A and B. Each of

the counters is associated with a memory page. A counter without external trigger input increments each

time data is written to the page it is associated with (write cycle counter). The counters triggered by

Pin Configurations appear at end

increment

inputs A and B, respectively,

of data sheet.

with every low-going pulse on their input. All counters are read-

Functional

only. They

Diagrams continued at

cleared to 0 when the battery is connected.

are automatically

end of data sheet.

UCSP is a trademark of Maxim Integrated Products, Inc.

1-Wire is a registered trademark of Dallas Semiconductor Corp., a

wholly owned subsidiary of Maxim Integrated Products Inc.

DESCRIPTION

For pricing, delivery, and ordering information, please contact Maxim Direct

at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.

1 of

PIN ASSIGNMENT

Ground

Data

Vbat

Input channel B

Input channel A

Compact, low cost 6-pin TSOC surface mount

package

Reads, writes and counts over a wide voltage

range of 2.8V to 5.5V from -40°C to +85°C

6-pin TSOC package

Tape & Reel Version of

DS2423P

6-pin TSOC package

080207

DS2423

OVERVIEW

PARASITE POWER

64-BIT LASERED ROM

Each DS2423 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code.

The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits (See Figure 3).

The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates

as shown in Figure 4. The polynomial is X

+ X

+ 1. Additional information about the Dallas 1-

Wire Cyclic Redundancy Check is available in Application Note 27. The shift register bits are initialized

to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the

bit of the family code has been entered, then the serial number is entered. After the 48

bit of the

serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of CRC

should return the shift register to all 0s.

The block diagram (Figure 1) shows the parasite-powered circuitry. This circuitry steals power whenever

the I/O input is high. I/O will provide sufficient power as long as the specified timing and voltage

requirements are met. The advantages of parasite power are two-fold: 1) by parasiting off this input,

lithium is conserved, and 2) if the battery is exhausted for any reason, the ROM may still be read

normally.

The block diagram in Figure 1 shows the relationships between the major control and memory sections of

the DS2423. The DS2423 has four main data components: 1) 64-bit lasered ROM, 2) 256-bit scratchpad,

3) 4096-bit SRAM, and 4) four 32-bit read-only counters. The hierarchical structure of the 1-Wire

protocol is shown in Figure 2. Each of these counters is associated with one of the 256-bit memory pages.

The four counters of the DS2423 are associated with pages 12 to 15. The contents of the counter are read

together with the memory data using a special command. The bus master must first provide one of the

six ROM Function Commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5)

Overdrive-Skip ROM or 6) Overdrive-Match ROM. Upon completion of an Overdrive ROM command

byte executed at standard speed, the device will enter Overdrive mode where all subsequent

communication occurs at a higher speed. The protocol required for these ROM function commands is

described in Figure 9. After a ROM function command is successfully executed, the memory functions

become accessible and the master may provide any one of the five memory function commands. The

protocol for these memory function commands is described in Figure 7. All data is read and written least

significant bit first.

2 of 25

The DS2423 1-Wire RAM with Counters can store encrypted data. The unique registration number and

the page write cycle counter(s) prevent unauthorized manipulation of data stored in a page with a write

cycle counter associated.

The battery-backed memory offers a simple solution to storing and retrieving information pertaining to

the equipment where the DS2423 is installed and its frequency of use. The scratchpad is an additional

page that acts as a buffer when writing to memory. Data is first written to the scratchpad where it may be

read back for verification. A copy scratchpad command will then transfer the data to memory. This

process ensures data integrity when modifying the memory. A 64-bit registration number is factory

lasered into each DS2423 to provide a guaranteed unique identity which allows for absolute traceability

and acts as node address if multiple DS2423 are connected in parallel to form a local network. Data is

transferred serially via the 1-Wire protocol, which requires only a single data lead and a ground return.

DS2423

BLOCK DIAGRAM

Figure 1

ADDRESS REGISTERS AND TRANSFER STATUS

Because of the serial data transfer, the DS2423 employs three address registers called TA1, TA2, and E/S

(Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data will be

written or from which data will be sent to the master upon a Read command. Register E/S acts like a byte

counter and Transfer Status register. It is used to verify data integrity with write commands. Therefore,

the master only has read access to this register. The lower 5 bits of the E/S register indicate the address of

the last byte that has been written to the scratchpad. This address is called Ending Offset. Bit 5 of the E/S

integer multiple of 8. Bit 6 has no function; it always reads 0. Note that the lowest 5 bits of the target

address also determine the address within the scratchpad, where intermediate storage of data will begin.

This address is called byte offset. If the target address (TA1) for a Write command is 03CH for example,

then the scratchpad will store incoming data beginning at the byte offset 1CH and will be full after only 4

bytes. The corresponding ending offset in this example is 1FH. For best economy of speed and efficiency,

the target address for writing should point to the beginning of a new page, i.e., the byte offset will be 0.

Thus the full 32-byte capacity of the scratchpad is available, resulting also in the ending offset of 1FH.

However, it is possible to write one or several contiguous bytes somewhere within a page. The ending

offset together with the Partial Flag support the master checking the data integrity after a Write command.

The highest valued bit of the E/S register, called AA or Authorization Accepted, acts as a flag to indicate

that the data stored in the scratchpad has already been copied to the target memory address. Writing data

to the scratchpad clears this flag.

3 of 25

DS2423

WRITING WITH VERIFICATION

Write Scratchpad Command [0FH]

The memory address range of the DS2423 is 0000H to 01FFH. If the bus master sends a target address

higher than this, the internal circuitry of the chip will set seven most significant address bits to 0 as they

are shifted into the internal address register. The Read Scratchpad command will reveal the target address

as it will be used by the DS2423. The master will identify such address modifications by comparing the

target address read back to the target address transmitted. If the master does not read the scratchpad, a

subsequent Copy Scratchpad command will not work since the most significant bits of the target address

the master sends will not match the value the DS2423 expects.

When executing the Write Scratchpad command the CRC generator inside the DS2423 (see Figure 12)

calculates a CRC over the entire data stream, starting at the command code and ending at the last data

byte sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC

generator and then shifting in the command code (0FH) of the Write Scratchpad command, the Target

Addresses TA1 and TA2 as supplied by the master and all the data bytes. The master may end the Write

Scratchpad command at any time. However, if the ending offset is 11111b, the master may send 16 read

time slots and will receive the CRC generated by the DS2423.

After issuing the Write Scratchpad command, the master must first provide the 2-byte target address,

followed by the data to be written to the scratchpad. The data will be written to the scratchpad starting at

the byte offset (T4:T0). The ending offset (E4: E0) will be the byte offset at which the master stops

writing data. Only full data bytes are accepted. If the last data byte is incomplete its content will be

ignored and the partial byte flag PF will be set.

The Memory Function Flow Chart (Figure 7) describes the protocols necessary for accessing the memory.

An example follows the flowchart. The communication between master and DS2423 takes place either at

regular speed (default, OD = 0) or at Overdrive speed (OD = 1). If not explicitly set into the Overdrive

mode the DS2423 assumes regular speed.

5 of 25

MEMORY FUNCTION COMMANDS

To write data to the DS2423, the scratchpad has to be used as intermediate storage. First the master issues

the Write Scratchpad command to specify the desired target address, followed by the data to be written to

the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an

inverted CRC16 of the command, address and data at the end of the Write Scratchpad command

sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to

decide if the communication was successful and proceed to the Copy Scratchpad command. If the master

could not receive the CRC16, it has to send the Read Scratchpad command to read back the scratchpad to

verify data integrity. As preamble to the scratchpad data, the DS2423 repeats the target address TA1 and

TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the

scratchpad. The master does not need to continue reading; it can start a new trial to write data to the

scratchpad. Similarly, a set AA flag indicates that the Write command was not recognized by the device.

If everything went correctly, both flags are cleared and the ending offset indicates the address of the last

byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After

the master has verified the data, it has to send the Copy Scratchpad command. This command must be

followed exactly by the data of the three address registers TA1, TA2 and E/S. The master may obtain the

contents of these registers by reading the scratchpad or derive it from the target address and the amount of

data to be written. As soon as the DS2423 has received these bytes correctly, it will copy the data to the

requested location beginning at the target address.

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