2.5V, 3.3V ECL/LVPECL Clock/Data
Fanout Buffer
General Description
The ICS853S9252I is a 2.5V/3.3V ECL/LVPECL fanout buffer
designed for high-speed, low phase-noise wireless infrastructure
applications. The device fanouts a differential input signal to two
ECL/LVPECL outputs. Optimized for low additive phase-noise,
sub-100ps output rise and fall times, low output skew and
high-frequencies, the ICS853S9252I is an effective solution for
high-performance clock and data distribution applications, for
instance driving the reference clock inputs of ADC/DAC circuits.
Internal input termination, a bias voltage output (V
REF
) for
AC-coupling and small packaging (3.0mm x 3.0mm 16-lead VFQFN)
supports space-efficient board designs.
The ICS853S9252I operates from a full 2.5V or 3.3V power supply
and supports the industrial temperature range of -40°C to 85°C. The
extended temperature range also supports wireless infrastructure,
tele-communication and networking end equipment requirements.
ICS853S9252I
DATASHEET
Features
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1:2 differential clock/data fanout buffer
Clock frequency: 3GHz (maximum)
Two differential 2.5V/3.3V ECL/LVPECL clock output
Differential input accepts ECL/LVPECL, LVDS and CML levels
Additive phase jitter, RMS @ 122.88MHz: 45fs (typical)
Propagation delay: 175ps (maximum), V
CC
= 3.3V
Output rise/fall time: 135ps (maximum), V
CC
= 3.3V
Internal input signal termination
Supply voltage: 2.5V-5% to 3.3V+10%
Lead-free (RoHS 6) packaging
-40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
50
Pin Assignment
VREF
VTT
V
CC
V
EE
Q0
nQ0
Q1
nQ1
16 15 14 13
IN
nIN
nc
nc
1
2
3
4
5 6
nc
nc
7
V
EE
8
VCC
12
11
10
9
Q0
nQ0
Q1
nQ1
VTT
VREF
VREF
Generator
ICS853S9252I
16 lead VFQFN
3.0mm x 3.0mm x 0.925mm
package body
K Package
Top View
ICS853S9252BKI JUNE 14, 2017
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©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Pin Descriptions
Table 1. Pin Descriptions
Number
1, 2
3, 4, 5, 6
7, 14
8, 13
9, 10
11, 12
15
16
Name
IN, nIN
nc
V
EE
V
CC
nQ1, Q1
nQ0, Q0
V
REF
V
TT
Type
Input
Unused
Power
Power
Output
Output
Output
Description
Non-inverting and inverting clock input. ECL/LVPECL, LVDS and CML interface levels. 50
to V
TT
or 100 input termination.
No connect.
Negative supply pins.
Power supply pins.
Differential clock output. ECL/LVPECL interface levels.
Differential clock output. ECL/LVPECL interface levels.
Bias voltage reference for AC-coupling of the differential inputs.
Center tap for input termination. Leave floating for LVDS inputs, connect 50 to GND for
3.3V LVPECL inputs and to the V
REF
output for AC-coupled applications.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the
DC Characteristics or AC
Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Negative Supply Voltage, V
EE
Inputs, V
I
(LVPECL mode)
Inputs, V
I
(ECL mode)
Outputs, I
O
Continuous Current
Surge Current
Input Current, IN, nIN
V
T
Current, I
VT
Input Sink/Source, I
REF
Operating Temperature Range, T
A
Package Thermal Impedance,
JA
, (Junction-to-Ambient)
Storage Temperature, T
STG
Rating
4.6V (LVPECL mode, V
EE
= 0V)
-4.6V (ECL mode, V
CC
= 0V)
-0.5V to V
CC
+ 0.5V
0.5V to V
EE
– 0.5V
50mA
100mA
±25mA
±50mA
±2mA
-40°C to +85°C
74.7C/W (0 mps)
-65C to 150C
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©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics,
V
CC
= 2.5V-5% to V
CC
= 3.3V+10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
CC
I
EE
Parameter
Power Supply Voltage
Power Supply Current
Output Supply Current
Includes load current
Test Conditions
Minimum
2.375
Typical
3.3
79
26
Maximum
3.63
99
33
Units
V
mA
mA
Table 2B. DC Characteristics,
V
CC
= 2.5V-5% to V
CC
= 3.3V+10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
REF
C
IN
Parameter
Input Resistance
Input High Voltage
Input Low Voltage
Input Voltage Swing
Differential Input
Voltage Swing
Bias Voltage Reference
Input Capacitance
Test Conditions
IN to V
TT
, nIN to V
TT
1.2
0
0.1
0.2
V
CC
– 1.3
2
Minimum
Typical
50
V
CC
V
IH
- 0.1
1.4
2.8
Maximum
Units
V
V
V
V
V
pF
Table 2C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.6
Typical
Maximum
V
CC
– 0.76
V
CC
– 1.6
1.1
Units
V
V
V
NOTE 1: The outputs are terminated with 50 to V
CC
– 2V.
Table 2D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
OH
V
OL
V
SWING
Parameter
Output High Voltage;
NOTE 1
Output Low Voltage;
NOTE 1
Peak-to-Peak Output
Voltage Swing
Test Conditions
Minimum
V
CC
– 1.4
V
CC
– 2.0
0.4
Typical
Maximum
V
CC
– 0.56
V
CC
– 1.5
1.1
Units
V
V
V
NOTE 1: The outputs are terminated with 50 to V
CC
– 2V.
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©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
AC Characteristics
Table 3. AC Characteristics,
V
CC
= 2.5V-5% to V
CC
= 3.3V+10%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
REF
t
PD
tsk(p)
tsk(o)
tsk(pp)
odc
tjit
Parameter
Input Reference Frequency
Propagation Delay, NOTE 1
Output Pulse Skew
Output Skew, NOTE 2, 3
Part-to-Part Skew, NOTE 3, 4
Output Duty Cycle
Buffer Additive Phase Jitter,
RMS; Refer to Additive Phase
Jitter Section
122.88MHz,
Integration Range:10Hz – 10MHz
122.88MHz, Offset: 10Hz
122.88MHz, Offset: 100Hz
Phase Noise Frequency
Offset
122.88MHz, Offset: 1kHz
122.88MHz, Offset: 10kHz
122.88MHz, Offset: 100kHz
122.88MHz, Offset: >1MHz
Power Supply Rejection;
NOTE 5
t
R
/ t
F
Output Rise/Fall Time
V
CC
= 3.3V
V
CC
= 3.3V, 20% to 80%
V
CC
= 2.5V, 20% to 80%
47
45
-98
-128
-150
-158
-161
-161
3
90
110
135
170
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
= 3.3V
V
CC
= 2.5V
75
85
135
130
Test Conditions
Minimum
Typical
Maximum
3
175
200
15
10
17
50
53
Units
GHz
ps
ps
ps
ps
ps
ps
%
fs
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
ps/V
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: All parameters characterized at f
REF
2GHz, unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
crosspoints.
NOTE 3: This parameter is defined according with JEDEC Standard 65.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 5: Change in t
PD
per change in V
CC
.
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©2017 Integrated Device Technology, Inc.
ICS853S9252I Datasheet
2.5V, 3.3V ECL/LVPECL CLOCK/DATA FANOUT BUFFER
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the
dBc Phase
Noise.
This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a
dBc
value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 122.88MHz
10Hz to 10MHz = 45fs (typical)
SSB Phase Noise (dBc/Hz)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
The source generator used is, low noise Wenzel Oscillator at
122.88MHz.
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©2017 Integrated Device Technology, Inc.
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