IXDF502 / IXDI502 / IXDN502
2 Ampere Dual Low-Side Ultrafast MOSFET Drivers
Features
• Built using the advantages and compatibility
of CMOS and IXYS HDMOS
TM
processes
• Latch-Up Protected up to 2 Amps
• High 2A Peak Output Current
• Wide Operating Range: 4.5V to 30V
•
-55°C
to +125°C Extended Operating
Temperature
• High Capacitive Load
Drive Capability: 1000pF in <10ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in Single Chip
General Description
The IXDF502, IXDI502 and IXDN502 each consist of two 2-
Amp CMOS high speed MOSFET Gate Drivers for driving
the latest IXYS MOSFETs & IGBTs. Each of the Dual
Outputs can source and sink 2 Amps of Peak Current while
producing voltage rise and fall times of less than 15ns. The
input of each Driver is TTL or CMOS compatible and is
virtually immune to latch up. Patented* design innovations
eliminate cross conduction and current "shoot-through".
Improved speed and drive capabilities are further enhanced
by very quick & matched rise and fall times.
The IXDF502 is configured with one Gate Driver Inverting
plus one Gate Driver Non-Inverting. The IXDI502 is config-
ured as a Dual Inverting Gate Driver, and the IXDN502 is
configured as a Dual Non-Inverting Gate Driver.
The IXDF502, IXDI502 and IXDN502 are each available in
the 8-Pin P-DIP (PI) package, the 8-Pin SOIC (SIA) pack-
age, and the 6-Lead DFN (D1) package, (which occupies
less than 65% of the board area of the 8-Pin SOIC).
Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Power Charge Pumps
*United States Patent 6,917,227
Ordering Information
Part Number
IXDF502PI
IXDF502SIA
IXDF502SIAT/R
IXDF502D1
IXDF502D1T/R
IXDI502PI
IXDI502SIA
IXDI502SIAT/R
IXDI502D1
IXDI502D1T/R
IXDN502PI
IXDN502SIA
IXDN502SIAT/R
IXDN502D1
IXDN502D1T/R
Description
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
2A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack Configuration
Qty
50
Dual, with one
94
Driver Inverting
2500 and one Driver
56
Non-Inverting
2500
50
Dual, with both
94
Drivers
2500
Inverting
56
2500
50
Dual, with both
94
Drivers Non-
2500
Inverting
56
2500
NOTE:
All parts are lead-free and RoHS Compliant
Copyright © 2007 IXYS CORPORATION All rights reserved
DS99573B(03/10)
First Release
IXDF502 / IXDI502 / IXDN502
Figure 1 - IXDF502 Inverting + Non-Inverting 2A Gate Driver Functional Block Diagram
Vcc
P
IN A
ANTI-CROSS
CONDUCTION
CIRCUIT *
*
OUT A
N
P
IN B
ANTI-CROSS
CONDUCTION
CIRCUIT *
*
OUT B
N
GND
Figure 2 - IXDI502 Dual Inverting 2A Gate Driver Functional Block Diagram
Vcc
P
IN A
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT A
N
*
P
IN B
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
N
*
GND
Figure 3 - IXDN502 Dual 2A Non-Inverting Gate Driver Functional Block Diagram
Vcc
P
IN A
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT A
N
P
IN B
ANTI-CROSS
CONDUCTION
CIRCUIT *
OUT B
N
GND
*
United States Patent 6,917,227
Copyright © 2007 IXYS CORPORATION All rights reserved
2
IXDF502 / IXDI502 / IXDN502
Absolute Maximum Ratings
(1)
Parameter
Supply Voltage
All Other Pins
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Value
35V
-0.3 V to V
CC
+ 0.3V
150
°
C
-65
°
C to 150
°
C
300
°
C
Operating Ratings
(2)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55
°
C to 125
°
C
Package Thermal Resistance
*
8-PinPDIP
(PI)
θ
J-A
(typ) 125
°
C/W
8-Pin SOIC
(SIA)
θ
J-A
(typ) 200
°
C/W
6-Lead DFN
(D1)
θ
J-A
(typ) 125-200
°
C/W
6-Lead DFN
(D1)
θ
J-C
(max) 3.3
°
C/W
6-Lead DFN
(D1)
θ
J-S
(typ)
7.3 °
C/W
Electrical Characteristics @ T
A
= 25
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V .
All voltage measurements with respect to GND. IXD_502 configured as described in
Test Conditions.
All specifications are for one channel.
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
PEAK
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
High state output
resistance
Low state output
resistance
Peak output current
Continuous output current
Rise time
Fall time
On-time propagation delay
Off-time propagation delay
Power supply voltage
Power supply current
Test Conditions
4.5V
≤
V
CC
≤
18V
4.5V
≤
V
CC
≤
18V
Min
3.0
(4)
Typ
Max
0.8
Units
V
V
V
µA
V
V
Ω
Ω
A
A
ns
ns
ns
ns
V
mA
µA
µA
-5
0V
≤
V
IN
≤
V
CC
-10
V
CC
- 0.025
V
CC
+ 0.3
10
0.025
V
CC
= 15V
V
CC
= 15V
V
CC
= 15V
C
LOAD
=1000pF V
CC
=15V
C
LOAD
=1000pF V
CC
=15V
C
LOAD
=1000pF V
CC
=15V
C
LOAD
=1000pF V
CC
=15V
4.5
V
IN
= 3.5V
V
IN
= 0V
V
IN
= +V
CC
2.5
2
2
4
3
1
7.5
6.5
25
20
15
1
0
10
9
32
30
30
3
15
15
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDF502 / IXDI502 / IXDN502
Electrical Characteristics @ temperatures over -55
o
C to 125
o
C
(3)
Unless otherwise noted, 4.5V
≤
V
CC
≤
30V , Tj < 150
o
C
All voltage measurements with respect to GND. IXD_502 configured as described in
Test Conditions.
All specifications are for one channel.
Symbol
V
IH
V
IL
V
IN
I
IN
V
OH
V
OL
R
OH
R
OL
I
DC
t
R
t
F
t
ONDLY
t
OFFDLY
V
CC
I
CC
Parameter
High input voltage
Low input voltage
Input voltage range
Input current
High output voltage
Low output voltage
High state output
resistance
Low state output
resistance
Continuous output
current
Rise time
Fall time
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
Power supply current
Test Conditions
4.5V
≤
V
CC
≤
15V
4.5V
≤
V
CC
≤
15V
Min
3.1
Typ
Max
0.8
Units
V
V
V
µA
V
V
Ω
Ω
A
ns
ns
ns
ns
V
mA
µA
µA
-5
0V
≤
V
IN
≤
V
CC
-10
V
CC
- 0.025
V
CC
+ 0.3
10
0.025
V
CC
= 15V
V
CC
= 15V
6
5
1
C
LOAD
=1000pF V
CC
=15V
C
LOAD
=1000pF V
CC
=15V
C
LOAD
=1000pF V
CC
=15V
C
LOAD
=1000pF V
CC
=15V
4.5
V
IN
= 3.5V
V
IN
= 0V
V
IN
= + V
CC
15
1
0
11
10
40
38
30
3
40
40
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
*
The following notes are meant to define the conditions for the
θ
J-A
,
θ
J-C
and
θ
J-S
values:
1) The
θ
J-A
(typ) is defined as junction to ambient. The
θ
J-A
of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with forced convection. For the 6-Lead DFN package, the
θ
J-A
value supposes the DFN package is
soldered on a PCB. The
θ
J-A
(typ) is 200
°
C/W with no special provisions on the PCB, but because the center pad provides a low
thermal resistance to the die, it is easy to reduce the
θ
J-A
by adding connected copper pads or traces on the PCB. These can reduce
the
θ
J-A
(typ) to 125
°
C/W easily, and potentially even lower. The
θ
J-A
for DFN on PCB without heatsink or thermal management will
vary significantly with size, construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no
thermal management.
2)
θ
J-C
(max) is defined as juction to case, where case is the large pad on the back of the DFN package. The
θ
J-C
values are generally not
published for the PDIP and SOIC packages. The
θ
J-C
for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The
θ
J-S
(typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
Copyright © 2007 IXYS CORPORATION All rights reserved
4
IXDF502 / IXDI502 / IXDN502
Pin Description
PIN
2
1
3
2
4
3
5
4
6
5
7
6
PACKAGE
SOIC, DIP
DFN
SOIC, DIP
DFN
SOIC, DIP
DFN
SOIC, DIP
DFN
SOIC, DIP
DFN
SOIC, DIP
DFN
SYMBOL
IN A
FUNCTION
A Channel Input
DESCRIPTION
A Channel Input signal-TTL or CMOS compatible.
The system ground pin. Internally connected to all circuitry,
this pin provides ground reference for the entire chip. This pin
should be connected to a low noise analog ground plane for
optimum performance.
B Channel Input signal-TTL or CMOS compatible.
B Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
Positive power-supply voltage input. This pin provides power
to the entire chip. The range for this voltage is from 4.5V to
30V.
A Channel Driver output. For application purposes, this pin is
connected via a resistor to a gate of a MOSFET/IGBT.
GND
Ground
IN B
OUT B
V
CC
OUT A
B Channel Input
B Channel Output
Supply Voltage
A Channel Output
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Pin Configuration
IXDF502
1
2
3
4
IXDI502
8
7
6
1
2
3
4
IXDN502
8
7
6
1
2
3
4
NC
IN A
GND
INB
NC
O UT A
V
S
NC
IN A
GND
INB
NC
O UT A
V
S
NC
IN A
GND
INB
NC
O UT A
V
S
8
7
6
O UT B 5
O UT B 5
O UT B 5
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDF402
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDI402
8 Lead PDIP (PI)
8 Pin SOIC (SI)
(SIA)
IXDN402
6 Lead DFN (D1)
(Bottom View)
6 OU A IN A 1
T
5
Vc c
GND 2
IN B 3
6 Lead DFN (D1)
(Bottom View)
6 OU A IN A 1
T
5 Vc c
4 OU B
T
GND 2
IN B 3
6 Lead DFN (D1)
(Bottom View)
6 OU A
T
5
Vc c
IN A 1
GND 2
IN B 3
4 OU B
T
4 OU B
T
NOTE:
Solder tabs on bottoms of DFN packages are grounded
Figure 4 - Characteristics Test Diagram
Vcc
10uF
0.01uF
1
NC
2
In A
3
Gnd
4
In B
NC
8
7
Out A
Vcc
6
Out B
5
Agilent 1147A
Current Probe
1000 pF
Agilent 1147A
Current Probe
1000 pF
IXYS reserves the right to change limits, test conditions, and dimensions.
5
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