71V25761S166PFGI8 datasheet, PDF

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71V25761S166PFGI8: DescriptionSRAM 4Mb PBSRAM 128K x 36 w/2.5V I/O Pipeline; Categorystorage storage; File Size263KB，21 Pages; ManufacturerIDT (Integrated Device Technology)

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71V25761S166PFGI8 Overview

SRAM 4Mb PBSRAM 128K x 36 w/2.5V I/O Pipeline

71V25761S166PFGI8 Parametric

Parameter Name	Attribute value
Maker	IDT (Integrated Device Technology)
package instruction	LQFP,
Reach Compliance Code	compliant
ECCN code	3A991.B.2.A
Maximum access time	3.5 ns
Other features	PIPELINED ARCHITECTURE
JESD-30 code	R-PQFP-G100
length	20 mm
memory density	4718592 bit
Memory IC Type	CACHE SRAM
memory width	36
Number of functions	1
Number of terminals	100
word count	131072 words
character code	128000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	128KX36
Package body material	PLASTIC/EPOXY
encapsulated code	LQFP
Package shape	RECTANGULAR
Package form	FLATPACK, LOW PROFILE
Parallel/Serial	PARALLEL
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.465 V
Minimum supply voltage (Vsup)	3.135 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm
Base Number Matches	1

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128K X 36

IDT71V25761YS/S

3.3V Synchronous SRAMs

2.5V I/O, Pipelined Outputs,

Burst Counter, Single Cycle Deselect

◆

Features

◆

128K x 36 memory configuration

Supports high system speed:

Commercial:

– 200MHz 3.1ns clock access time

Commercial and Industrial:

– 183MHz 3.3ns clock access time

– 166MHz 3.5ns clock access time

LBO

input selects interleaved or linear burst mode

Self-timed write cycle with global write control (GW), byte write

enable (BWE), and byte writes (BWx)

3.3V core power supply

Power down controlled by ZZ input

2.5V I/O

Optional - Boundary Scan JTAG Interface (IEEE 1149.1

Compliant)

Packaged in a JEDEC Standard 100-pin plastic thin quad

flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball

grid array

Description

The IDT71V25761 are high-speed SRAMs organized as 128K x 36.

The IDT71V25761 SRAMs contain write, data, address and control

registers. Internal logic allows the SRAM to generate a self-timed write

based upon a decision which can be left until the end of the write cycle.

The burst mode feature offers the highest level of performance to the

system designer, as the IDT71V25761 can provide four cycles of data for

a single address presented to the SRAM. An internal burst address

counter accepts the first cycle address from the processor, initiating the

access sequence. The first cycle of output data will be pipelined for one

cycle before it is available on the next rising clock edge. If burst mode

operation is selected (ADV=LOW), the subsequent three cycles of output

data will be available to the user on the next three rising clock edges. The

order of these three addresses are defined by the internal burst counter

and the

LBO

input pin.

The IDT71V25761 SRAMs utilize IDT’s latest high-performance

CMOS process and are packaged in a JEDEC standard 14mm x 20mm

100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array

(BGA) and 165 fine pitch ball grid array (fBGA).

Pin Description Summary

-A

BWE

(1)

CLK

ADV

ADSC

ADSP

LBO

TMS

TDI

TCK

TDO

TRST

I/O

-I/O

, I/O

-I/O

, V

DDQ

Address Inputs

Chip Enable

Chip Selects

Output Enable

Global Write Enable

Byte Write Enable

Individual Byte Write Selects

Clock

Burst Address Advance

Address Status (Cache Controller)

Address Status (Processor)

Linear / Interleaved Burst Order

Test Mode Select

Test Data Input

Test Clock

Test Data Output

JTAG Reset (Optional)

Sleep Mode

Data Input / Output

Core Power, I/O Power

Ground

Input

Output

Input

I/O

Supply

Synchronous

Asynchronous

Synchronous

N/A

Synchronous

N/A

Synchronous

Asynchronous

Synchronous

N/A

5297 tbl 01

JULY 2014

DSC-5297/06

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