Micrel, Inc.
ULTRA PRECISION DUAL 2:1 LVPECL
MUX WITH INTERNAL TERMINATION
Precision Edge
®
SY58026U
Precision Edge
®
SY58026U
FEATURES
Two independent differential 2:1 multiplexers
Guaranteed AC performance over temperature and
voltage:
• DC-to >5Gbps data rate throughput
• <310ps IN-to-Out t
pd
• <110ps t
r
/ t
f
Unique, patent-pending input isolation design
minimizes crosstalk
Ultra-low jitter design:
• <1ps
RMS
random jitter
• <10ps
PP
deterministic jitter
• <10ps
PP
total jitter (clock)
• <0.7ps
RMS
crosstalk-induced jitter
Unique, patent-pending 50½ input termination and
VT pin accepts DC-coupled and AC-coupled inputs
(CML, LVDS, PECL)
800mV LVPECL output swing
Power supply 2.5V ±5% or 3.3V ±10%
–40°C to +85°C temperature range
Available in 32-pin (5mm
∞
5mm) MLF
®
package
Precision Edge
®
DESCRIPTION
The SY58026U features two ultra-fast, low jitter 2:1
differential muxes with a guaranteed maximum data
throughput of 5Gbps.
The SY58026U differential inputs include a unique
internal termination design that allows access to the
termination network through a VT pin. The device easily
interfaces to different logic standards, both AC- and DC-
coupled, without external resistor-bias and termination
networks. The result is a clean, stub-free, low jitter interface
solution. The differential 800mV LVPECL outputs have
extremely fast rise/fall times guaranteed to be less than
110ps.
The SY58026U operates from a 2.5V or 3.3V supply,
and is guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY58026U is part of Micrel’s Precision
Edge
®
product family.
All support documentation can be found on Micrel’s web
site at www.micrel.com.
APPLICATIONS
Data communication systems
SONET applications
Fibre Channel applications
GigE applications
FUNCTIONAL BLOCK DIAGRAM
INA0
50Ω
V
TA0
50Ω
/INA0
V
REF-ACA0
INA1
50Ω
V
TA1
50Ω
/INA1
V
REF-ACA1
SELA
(TTL/CMOS)
1
S
MUX A
0
INB0
50Ω
V
TB0
50Ω
0
QA
/QA
/INB0
V
REF-ACB0
INB1
50Ω
V
TB1
50Ω
/INB1
V
REF-ACB1
SELB
(TTL/CMOS)
1
S
MUX B
QB
/QB
United States Patent No. RE44,134
AnyGate and Precision Edge are registered trademarks of Micrel, Inc.
MicroLeadFrame
and MLF are trademarks of Amkor Technology, Inc.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
Rev.: E
Amendment: /0
1
Issue Date: August 2007
Micrel, Inc.
Precision Edge
®
SY58026U
PACKAGE/ORDERING INFORMATION
/INA1
VREF-ACA1
VTA1
INA1
/INA0
VREF-ACA0
VTA0
INA0
Ordering Information
(1)
Part Number
SY58026UMI
GND
VCC
QA
/QA
VCC
NC
SELA
VCC
Package
Type
MLF-32
MLF-32
MLF-32
MLF-32
Operating
Range
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY58026U
SY58026U
SY58026U with
Pb-Free bar-line indicator
SY58026U with
Pb-Free bar-line indicator
Lead
Finish
Sn-Pb
Sn-Pb
Pb-Free
NiPdAu
Pb-Free
NiPdAu
INB0
VTB0
VREF-ACB0
/INB0
INB1
VTB1
VREF-ACB1
/INB1
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
9
17
10 11 12 13 14 15 16
SY58026UMITR
(2)
SY58026UMG
SY58026UMGTR
(2)
Notes:
GND
VCC
/QB
QB
VCC
NC
SELB
VCC
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Tape and Reel.
32-Pin MLF
®
(MLF-32)
PIN DESCRIPTION
Pin Number
25, 28,
29, 32,
1, 4,
5, 8
Pin Name
INA0, /INA0,
INA1, /INA1,
INB0, /INB0,
INB1, /INB1
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs
accept AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair internally
terminates to a VT pin through 50½. Note that these inputs will default to an indeterminate
state if left open. Unused differential input pairs can be terminated by connecting one input
to V
CC
and the complementary input to GND through a 1k½ resistor. The VT pin is to be
left open in this configuration. Please refer to the “Input Interface Applications” section for
more details.
Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT
pin. Each VT pin provides a center-tap to a termination network for maximum interface
flexibility. See “Input Interface Applications” section for more details.
Bank A, Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs
select the inputs to the multiplexers. These inputs are internally connected to a 25k½
pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold
is V
CC
/2.
Reference Output Voltage: These outputs bias to V
CC
–1.2V. Connect to VT pin when
AC-coupling the data inputs. Bypass with 0.01µF low ESR capacitor to V
CC
.
Maximum current source or sink is 0.5mA. See “Input Interface Applications” section.
Positive Power Supply: Bypass with 0.1µF™ℑ0.01µF low ESR capacitors.
Differential 100k LVPECL Outputs: MUX A and MUX B selected LVPECL outputs.
See “Output Interface Applications” section for termination. Refer to the “Truth Table” for
logic operation.
Ground: Ground pins and exposed pad must be connected to the same ground plane.
Not connected.
26, 30, 2, 6
VTA0 , VTA1,
VTB0, VTB1
SELA, SELB
18, 15
27, 31, 3, 7
VREF-ACA0,
VREF-ACA1,
VREF-ACB0,
VREF-ACB1
VCC
QA, /QA,
QB, /QB
GND,
Exposed pad
NC
10, 13, 16,
17, 20, 23
22, 21,
12, 11
9, 24
14, 19
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY58026U
Absolute Maximum Ratings
(1)
Power Supply Voltage (V
CC
) ...................... –0.5V to +4.0V
Input Voltage (V
IN
) .......................................... –0.5V to V
CC
LVPECL Output Current (I
OUT
)
Continuous .............................................................. 50mA
Surge ....................................................................100mA
Termination Current
(3)
Source or sink current on V
T ......................................
±100mA
Input Current
Source or sink current on IN, /IN .......................... ±50mA
Current (V
REF-AC
)
Source or sink current on V
REF-AC(3)
................... ±1.5mA
Lead Temperature (soldering, 20 sec.) ..................... 260°C
Storage Temperature Range (T
S
) ........... –65°C to +150°C
Operating Ratings
(2)
Power Supply Voltage (V
CC
) ............... +2.375V to +2.625V
............................................................. +3.0V to +3.6V
Ambient Temperature Range (T
A
) .............. –40°C to +85°C
Package Thermal Resistance
(4)
MLF
®
(θ
JA
)
Still-Air ............................................................. 35°C/W
MLF
®
(ψ
JB
)
Junction-to-board ............................................ 20°C/W
DC ELECTRICAL CHARACTERISTICS
(5)
T
A
= –40°C to +85°C; unless otherwise stated.
Symbol
V
CC
I
CC
R
DIFF_IN
R
IN
V
IH
V
IL
V
IN
V
DIFF_IN
V
T_IN
V
REF-AC
Parameter
Power Supply
Power Supply Current
Differential Input Resistance
(IN-to-/IN)
Input Resistance
(IN-to-V
T
, /IN-to-V
T
)
Input High Voltage (IN, /IN)
Input Low Voltage (IN, /IN)
Input Voltage Swing (IN, /IN)
Differential Input Voltage Swing
|IN – /IN|
In-to-V
T
(IN, /IN)
Output Reference Voltage
See Figure 1a.
See Figure 1b.
Note 6
Condition
V
CC
= 2.5V
V
CC
= 3.3V
No load, max. V
CC
.
80
40
V
CC
–1.6
0
0.1
0.2
1.28
V
CC
–1.3 V
CC
–1.2 V
CC
–1.1
Min
2.375
3.0
Typ
2.5
3.3
100
100
50
Max
2.625
3.6
130
120
60
V
CC
V
IH
–0.1
1.7
Units
V
V
mA
½
½
V
V
V
V
V
V
Notes:
1. Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for
extended periods may affect device reliability.
2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3. Due to the limited drive capability, use for input of the same package only.
4. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device’s most negative potential (GND) on the PCB.
Ψ
JB
uses
4-layer
θ
JA
in still air unless otherwise stated.
5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
6. V
IH
(min) not lower than 1.2V.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY58026U
LVPECL OUTPUT DC ELECTRICAL CHARACTERISTICS
(6)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to +85°C; R
L
= 50½ to V
CC
–2V, unless otherwise stated.
Symbol
V
OH
V
OL
V
OUT
V
DIFF-OUT
Parameter
Output High Voltage
Q, /Q
Output Low Voltage
Q, /Q
Output Voltage Swing
Q, /Q
Differential Output Voltage Swing
Q, /Q
See Figure 1a.
See Figure 1b.
Condition
Min
V
CC
–1.145
V
CC
–1.945
550
1100
800
1600
Typ
Max
V
CC
–0.895
V
CC
–1.695
Units
V
V
mV
mV
LVTTL/CMOS DC ELECTRICAL CHARACTERISTICS
(6)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to 85°C unless otherwise stated.
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
V
IL
= 0V
–175
–300
Condition
Min
2.0
0.8
75
Typ
Max
Units
V
V
µA
µA
Note:
6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge
®
SY58026U
AC ELECTRICAL CHARACTERISTICS
(7)
V
CC
= 2.5V ±5% or 3.3V ±10%; T
A
= –40°C to +85°C; R
L
= 50½ to V
CC
–2V, unless otherwise stated.
Symbol
f
MAX
t
pd
t
SKEW
Parameter
Maximum Operating Frequency
V
OUT
ž 400mV
Propagation Delay
IN-to-Q
SEL-to-Q
Input-to-Input Skew (Within-bank)
Bank-to-Bank Skew
Part-to-Part Skew
t
JITTER
Data
Clock
Random Jitter (RJ)
Deterministic Jitter (DJ)
Cycle-to-Cycle Jitter (RJ)
Total Jitter (TJ)
Crosstalk-induced Jitter
Channel-to-Channel (Within-bank)
t
r
, t
f
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. V
IN
swing ž 100mV unless otherwise noted.
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 2
23
–1 PRBS pattern
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, T
n
–T
n–1
where T is the time between rising edges of the output
signal.
14. Total jitter definition: with an ideal clock input of frequency - f
MAX
, no more than one output edge in 10
12
output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
Condition
NRZ Data
Clock
Min
5
Typ
6
Max
Units
Gbps
GHz
V
IN
ž 300mV
Note 8
Note 9
Note 10
Note 11
Note 12
Note 13
Note 14
Note 15,
Within-bank.
At full swing.
160
100
230
220
7
8
310
400
15
20
100
1
10
1
10
0.7
ps
ps
ps
ps
ps
ps
RMS
ps
PP
ps
RMS
ps
PP
ps
RMS
ps
Output Rise/Fall Time 20% to 80%
35
70
110
TRUTH TABLES
INA0
0
1
X
X
INB0
0
1
X
X
/INA0
1
0
X
X
/INB0
1
0
X
X
INA1
X
X
0
1
INB1
X
X
0
1
/INA1
X
X
1
0
/INB1
X
X
1
0
SELA
0
0
1
1
SELB
0
0
1
1
QA
0
1
0
1
QB
0
1
0
1
/QA
1
0
1
0
/QB
1
0
1
0
M9999-082707
hbwhelp@micrel.com or (408) 955-1690
5
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