The DG221B is a monolithic quad single-pole, single-throw
analog switch designed for precision switching applications
in communication, instrumentation and process control
systems.
Featuring independent onboard latches and a common WR
pin, each DG221B can be memory mapped, and addressed
as a single data byte for simultaneous switching.
The DG221B combines low power and low on-resistance
(60 typical) while handling continuous currents up to 20 mA.
An epitaxial layer prevents latchup.
The device features true bidirectional performance in the on
condition.
FEATURES
• Accepts 150 ns write pulse width
• 5 V on-chip regulator
• Latches are transparent with WR low
Pb-free
Available
RoHS*
COMPLIANT
•
Low on-resistance: 60 W
BENEFITS
• Compatible with most µP buses
• Allows wide power supply tolerance without affecting TTL
compatibility
• Reduced power consumption
• Allows flexibility of design
APPLICATIONS
• µP based systems
• Automatic test equipment
• Communication systems
• Data acquisition systems
• Medical instrumentation
• Factory automation
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
Dual-In-Line and SOIC
Four latchable SPST switches per package
TRUTH TABLE
IN
1
D
1
S
1
V-
GND
S
4
D
4
IN
4
1
2
3
Input Latch
4
5
6
7
8
16
15
14
13
12
11
10
9
IN
2
D
2
S
2
V+
WR
S
3
D
3
IN
3
IN
X
0
1
X
X
Logic "0"
≤
0.8 V
Logic "1"
≥
2.4 V
WR
0
0
Switch
ON
OFF
Control data latched-in, switches on
or off as selected by last IN
X
1
Maintains previous state
Top View
* Pb containing terminations are not RoHS compliant, exemptions may apply.
Document Number: 71616
S-80263-Rev. B, 11-Feb-08
www.vishay.com
1
DG221B
Vishay Siliconix
ORDERING INFORMATION
Temp. Range
- 40 °C to 85 °C
Package
16-Pin Plastic DIP
16-Pin Narrow SOIC
Standard Part Number
DG221BDJ
DG221BDY
DG221BDY-T1
Lead (Pb)-free Part Number
DG221BDJ-E3
DG221BDY-E3
DG221BDY-T1-E3
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltages Referenced V+ to V-
GND
Digital Inputs , V
S
, V
D
Continuous Current (Any Terminal)
Continuous Current, S or D
Peak Current, S or D (Pulsed at 1 ms, 10 % duty cycle max.)
Storage Temperature
Power Dissipation (Package)
b
(DJ and DY Suffix)
16-Pin Plastic
16-Pin SOIC
d
DIP
c
a
Limit
34
25
(V-) - 2 to (V+) + 2
or 20 mA, whichever occurs first
30
20
70
- 65 to 125
470
600
Unit
V
mA
°C
mW
Notes:
a. Signals on S
X
, D
X
, or IN
X
exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 6.5 mW/°C above 25 °C.
d. Derate 7.7 mW/°C above 75 °C.
SCHEMATIC DIAGRAM
Typical Channel
V+
5V
Reg
GND
IN
X
-
+
V-
V+
WR
-
+
V-
Latch
Level
Shift/
Drive
V+
S
D
V-
Figure 1.
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2
Document Number: 71616
S-80263-Rev. B, 11-Feb-08
DG221B
Vishay Siliconix
SPECIFICATIONS
a
Test Conditions
Unless Otherwise Specified
V+ = 15 V, V- = - 15 V
V
IN
= 2.4 V, 0.8 V
f
, WR = 0
Limits
- 40 °C to 85 °C
Temp.
b
Full
I
S
= - 10 mA, V
D
= ± 10 V
Room
Full
Room
Full
Room
Full
Room
Full
Room
Full
Room
Room
Room
Room
Room
See Figure 4
C
L
= 1000 pF, V
gen
= 0 V, R
gen
= 0
Ω
f = 1 MHz, V
S
, V
D
= 0 V
V
S
= 1 V
p-p
, f = 100 kHz
C
L
= 15 pF, R
L
= 1 kΩ
All Channels On or Off
V
IN
= 0 V or 2.4 V
Room
Room
Room
Room
Room
Room
Room
Room
Full
Room
-1
150
180
20
120
130
18
20
8
9
29
70
90
0.8
- 0.4
1.5
dB
pF
pC
-5
- 100
-5
- 100
-5
- 200
-1
- 10
Min.
d
- 15
60
± 0.01
± 0.02
± 0.01
Typ.
c
Max.
d
15
90
135
5
100
5
100
5
200
1
10
550
340
550
340
ns
nA
Unit
V
Ω
Parameter
Analog Switch
Analog Signal Range
e
Drain-Source
On-Resistance
Source Off Leakage Current
Drain Off Leakage Current
Drain On Leakage Current
Digital Control
Input Current
Dynamic Characteristics
Turn-On Time
Turn-Off Time
Turn-On Time Write
Turn-Off Time Write
Write Pulse Width
Input Setup Time
Input Hold Time
Charge Injection
Source-Off Capacitance
Drain-Off Capacitance
Channel On Capacitance
Off-Isolation
Interchannel Crosstalk
Power Supplies
Positive Supply Current
Negative Supply Current
Symbol
V
ANALOG
r
DS(on)
I
S(off)
V
S
= ± 14 V, V
D
= ± 14 V
I
D(off)
I
D(on)
V
S
= V
D
= ± 14 V
I
INL
, I
INH
V
IN
= 0 V or = 2.4 V
- 0.0004
µA
t
ON
t
OFF
t
ON
, WR
t
OFF
, WR
t
W
t
S
t
H
Q
C
S(off)
C
D(off)
C
D(on)
OIRR
X
TALK
I+
I–
See Figure 2
See Figure 3
mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25 °C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. V
IN
= input voltage to perform proper function.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 71616
S-80263-Rev. B, 11-Feb-08
www.vishay.com
3
DG221B
Vishay Siliconix
TEST CIRCUITS
+ 15 V
V+
2V
S
IN
GND
WR
V-
R
L
1 kΩ
C
L
35 pF
D
V
O
Logic
Input
3V
50 %
0V
t
r
< 10 ns
t
f
< 10 ns
Switch
Input
Switch
Output
V
S
90 %
V
O
t
ON
t
OFF
- 15 V
C
L
(includes fixture and stray capacitance)
V
O
= V
S
R
L
R
L
+ r
DS(on)
Figure 2. Switching Time
+ 15 V
0V
WR
2V
S
IN
GND
V-
R
L
1 kΩ
C
L
35 pF
V
OUT
- 15 V
C
L
(includes fixture and stray capacitance)
V
O
= V
S
R
L
R
L
+ r
DS(on)
V
O
t
ON
, WR
t
OFF
, WR
V
S
90 %
V+
D
V
O
IN
3V
WR
0V
3V
0V
t
r
< 10 ns
t
f
< 10 ns
50 %
Figure 3. WR Switching Time
3V
50 %
IN
t
S
3V
50 %
WR
t
W
t
H
= Hold Time
t
S
= Setup Time
t
W
= WR Pulse Width
t
H
t
S
t
H
VOUT
Figure 4. WR Setup Conditions
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4
Document Number: 71616
S-80263-Rev. B, 11-Feb-08
DG221B
Vishay Siliconix
TEST CIRCUITS
+ 15 V
ΔV
O
R
g
V
g
3V
WR
V-
V+
S
IN
D
V
O
C
L
1000 pF
V
O
IN
X
OFF
ON
OFF
- 15 V
ΔV
O
= measured voltage error due to charge injection
The charge injection in coulombs is Q = C
L
x
ΔV
O
Figure 5. Charge Injection
C
+ 15 V
C
+ 15 V
V+
V
S
V+
S
1
R
g
= 50
Ω
IN
1
0V
S
2
D
1
50
Ω
V
S
R
g
= 50
Ω
2.4 V
S
D
V
O
IN
GND
WR
V-
C
R
L
NC
0V
D
2
R
L
GND
WR
V-
C
V
O
IN
2
- 15 V
- 15 V
V
S
V
O
X
TA LK
Isolation = 20 log
C = RF bypass
Off Isolation = 20 log
C = RF bypass
V
S
V
O
Figure 6. Off Isolation
Figure 7. Channel-to-Channel Crosstalk
APPLICATION HINTS
a
V+
Positive Supply
Voltage
(V)
15
10
10
V-
Negative Supply
Voltage
(V)
- 15
- 10
-5
GND
(V)
0
0
0
WR
(V)
2.4/0.8
2.4/0.8
2.4/0.8
V
IN
Logic Input Voltage
V
INH(min)
/V
INL(max)
(V)
2.4/0.8
2.4/0.8
2.4/0.8
V
S
or V
D
Analog Voltage
Range
(V)
- 15 to 15
- 10 to 10
- 5 to 10
Notes:
a. Application hints are for DESIGN AID ONLY, not guaranteed and not subject to production testing.
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