DATASHEET
32-pin CK505 for Intel Systems
Recommended Application:
CK505 clock, 32-pin for 5 series Intel chipsets
Output Features:
•
1 - CPU differential low power push-pull pairs
•
1 - SRC differential low power push-pull pairs
•
1 - Selectable 120MHz CK_SSC_Disp or 100 MHz SRC low
power push-pull pair
•
1 - SATA/SRC selectable differential low power push-pull pair
•
1 - DOT differential low power push-pull pair
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
+/- 100ppm frequency accuracy on all outputs
•
SRC are PCIe Gen2 compliant
ICS9LRS4103
Features/Benefits:
•
Supports spread spectrum modulation, default is 0.5%
down spread
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Does not require external pass transistor for voltage
regulator
•
Integrated 33Ω series resistors on differential outputs,
Zo=50Ω
Table 1: CPU Frequency Select Table
Pin Configuration
REF14.318M/FSLC**
CKPWRGD/PD#_3.3
SEL_SATA_NS#
GNDXTAL
VDDXTAL
100.00
14.318 96.00
VDDREF14M
1. FS
L
C is a low-threshold input.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
X1 1
32 31 30 29 28 27 26 25
24 CPUC0
23 CPUT0
22 GNDCPU
X2 2
SMBCLK_3.3 3
SEL_120M#
Pin# 21
Pulled Low
Pulled High
Pin# 10/11
120MHz
100MHz
SMBDAT_3.3 4
VDD96 5
DOT96T 6
DOT96C 7
GND96 8
9
GNDSSC
VDDCPU
21 SEL_120M#
20 VDDSRC
19 SRC2C
18 SRC2T
17 GNDSRC
GNDSATA
9LRS4103
CK_SSC_DISP_C
CK_SSC_DISP_T
VDDSSC
SRC1T/SATA_NS_T
VDDSATA
SEL_SATA_NS#
Pin# 31
0
1
Pin# 14/15
100MHz_nonSS
100MHz_SS
10 11 12 13 14 15 16
SRC1C/SATA_NS_C
** Internal Pull-Down Resistor
IDT
®
PC MAIN CLOCK
GNDREF
FS
L
C
B0b7
0 (Default)
1
CPU
MHz
133.33
100.00
SRC
MHz
REF
MHz
DOT
MHz
1520A—03/16/10
1
ICS9LRS4103
PC MAIN CLOCK
Pin Description
Pin#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Pin Name
X1
X2
SMBCLK_3.3
SMBDAT_3.3
VDD96
DOT96T
DOT96C
GND96
GNDSSC
CK_SSC_DISP_T
CK_SSC_DISP_C
VDDSSC
VDDSATA
SRC1T/SATA_NS_T
SRC1C/SATA_NS_C
GNDSATA
GNDSRC
SRC2T
SRC2C
VDDSRC
SEL_120M#
GNDCPU
Type Pin Description
IN
Crystal input, Nominally 14.318MHz.
OUT
IN
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
IN
Crystal output, Nominally 14.318MHzMHz.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Power pin for the DOT96MHz output 3.3V.
True clock DOT96 output with integrated 33ohm series resistor. No 50ohm
resistor to GND needed.
Complementary clock DOT96 output with integrated 33ohm series resistor.
No 50ohm resistor to GND needed.
Ground pin for the DOT96MHz output.
Ground pin for the CK_SSC_DISP output.
True clock of CK_SSC_DISP (100MHz or 120MHz) output with integrated
33ohm series resistor. No 50ohm resistor to GND needed.
Complementary clock of CK_SSC_DISP (100MHz or 120MHz) output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
Power pin for the CK_SSC_DISP output 3.3V
Power pin for the SATA output 3.3V
True clock of differential 0.8V push-pull SRC/SATA output with integrated
33ohm series resistor. No 50ohm resistor to GND needed.
Complementary clock of differential 0.8V push-pull SRC/SATA output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
Ground pin for the SATA output.
Ground pin for the SRC output.
True clock of differential 0.8V push-pull SRC output with integrated 33ohm
series resistor. No 50ohm resistor to GND needed.
Complementary clock of differential 0.8V push-pull SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND needed.
Power pin for the SRC output 3.3V.
Selects pins #10/11 to be 120MHz or 100MHz. "0" = 120MHz, "1" = 100MHz.
PWR Ground pin for the CPU output.
True clock of differential pair 0.8V push-pull CPU outputs with integrated
CPUT0
OUT
33ohm series resistor. No 50 ohm resistor to GND needed.
Complementary clock of differential pair 0.8V push-pull CPU outputs with
CPUC0
OUT
integrated 33ohm series resistor. No 50 ohm resistor to GND needed.
VDDCPU
PWR Power pin for the CPU output 3.3V
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN#
CKPWRGD/PD#_3.3
IN
mode
VDDREF14M
PWR Power pin for the REF output 3.3V
Reference 14.318 MHz clock, which drives 3 loads on default / 3.3V tolerant
REF14.318M_3X/FSLC** I/O input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values.
GNDREF
PWR Ground pin for the REF output.
VDDXTAL
PWR Power pin for XTAL 3.3V
SEL_SATA_NS#
IN
Selects pin #14/15 to be SRC1 or SATA_NS. "0" = SATA_NS, "1" = SRC1
GNDXTAL
PWR Ground pin for XTAL.
IDT
®
PC MAIN CLOCK
1520A—03/16/10
2
ICS9LRS4103
PC MAIN CLOCK
AC Electrical Characteristics - Input/Common Parameters
PARAMETER
Clk Stabilization
Tfall_PD#
Trise_PD#
SYMBOL
TSTAB
TFALL
TRISE
CONDITIONS
From VDD Power-Up or de-assertion of
PD# to 1st clock
Fall/rise time of PD#, PCI_STOP# and
CPU_STOP# inputs
MIN
MAX
1.8
5
5
UNITS
ms
ns
ns
Notes
1
1
1
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
Maximum Output Voltage
Minimum Output Voltage
Differential Voltage Swing
Crossing Point Voltage
SYMBOL
tSLR
tFLR
tSLVAR
VHIGH
VLOW
VSWING
VXABS
CONDITIONS
Differential Measurement
Differential Measurement
Single-ended Measurement
Includes overshoot
Includes undershoot
Differential Measurement
Single-ended Measurement
Single-ended Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement
Differential Measurement, all SRC from
same PLL
45
MIN
2.5
2.5
MAX
4
4
20
1150
UNITS
V/ns
V/ns
%
mV
mV
mV
mV
mV
%
ps
ps
ps
ps
NOTES
1,2
1,2
1
1
1
1
1,3,4
1,3,5
1
1
1
1
1
-300
300
300
550
140
55
85
125
250
200
Crossing Point Variation VXABSVAR
Duty Cycle
CPU Jitter - Cycle to
Cycle
SRC Jitter - Cycle to
Cycle
DOT Jitter - Cycle to
Cycle
SRC Skew
DCYC
CPUJC2C
SRCJC2C
DOTJC2C
SRCSKEW
Electrical Characteristics - REF-14.318MHz
PARAMETER
Long Accuracy
Clock period
Absolute min/max period
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter
SYMBOL
ppm
Tperiod
Tabs
VOH
VOL
IOH
IOL
tSLR
tFLR
dt1
tjcyc-cyc
CONDITIONS
see Tperiod min-max values
14.318180 MHz output nominal
14.318180 MHz including cycle to cycle
jitter
IOH = -1 mA
IOL = 1 mA
VOH @MIN = 1.0 V,
VOH@MAX = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
VT = 1.5 V
VT = 1.5 V
MIN
0
69.8413
MAX
0
69.8413
UNITS
ppm
ns
ns
V
V
mA
mA
V/ns
V/ns
%
ps
Notes
1,6
6
6
1
1
1
1
1
1
1
1
68.8413 70.84128
2.4
0.4
-33
30
1
1
45
-33
38
4
4
55
1000
IDT
®
PC MAIN CLOCK
1520A—03/16/10
5
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