MC100LVEL01
3.3 V ECL 4-Input OR/NOR
Description
The MC100LVEL01 is a 4-input OR/NOR gate. The device is
functionally equivalent to the EL01 device and works from a 3.3 V
supply. With AC performance similar to the EL01 device, the LVEL01
is ideal for low voltage applications which require the ultimate in
AC performance.
Features
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•
370 ps Propagation Delay
•
High Bandwidth Output Transitions
•
ESD Protection:
♦
8
1
SOIC−8
D SUFFIX
CASE 751
8
1
TSSOP−8
DT SUFFIX
CASE 948R
•
•
•
•
•
•
•
•
•
•
> 2 kV Human Body Model
♦
> 200 V Machine Model
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
CC
= 3.0 V to 3.8 V
with V
EE
= 0 V
NECL Mode Operating Range: V
CC
= 0 V
with V
EE
=
−3.0
V to
−3.8
V
Internal Input Pulldown Resistors
Q Output will Default LOW with All Inputs Open or at V
EE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity
♦
Level 1 for SOIC−8
♦
Level 3 for TSSOP−8
♦
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index 28 to 34
Transistor Count = 83 Devices
These Devices are Pb-Free and are RoHS Compliant
MARKING DIAGRAMS*
8
KVL01
ALYW
G
1
SOIC−8
A
L
Y
W
M
G
1
8
KV01
ALYWG
G
TSSOP−8
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note
AND8002/D.
ORDERING INFORMATION
Device
MC100LVEL01DG
MC100LVEL01DR2G
MC100LVEL01DTG
Package
SOIC−8
(Pb-Free)
SOIC−8
(Pb-Free)
Shipping†
98 Units / Tube
2500
Tape & Reel
TSSOP−8 100 Units / Tube
(Pb-Free)
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure,
BRD8011/D.
©
Semiconductor Components Industries, LLC, 2016
July, 2016
−
Rev. 5
1
Publication Order Number:
MC100LVEL01/D
MC100LVEL01
Table 1. PIN DESCRIPTION
D
0
1
8
V
CC
PIN
D0−D3
Q, Q
V
CC
V
EE
FUNCTION
ECL Data Inputs
ECL Data Outputs
Positive Supply
Negative Supply
D
1
2
7
Q
D
2
3
6
Q
D
3
4
5
V
EE
Figure 1. Logic Diagram and Pinout Assignment
Table 2. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
I
out
T
A
T
stg
q
JA
q
JC
q
JA
q
JC
T
sol
Parameter
PECL Mode Power Supply
NECL Mode Power Supply
PECL Mode Input Voltage
NECL Mode Input Voltage
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Thermal Resistance (Junction-to-Ambient)
Thermal Resistance (Junction-to-Case)
Wave Solder (Pb-Free)
0 lfpm
500 lfpm
Standard Board
0 lfpm
500 lfpm
Standard Board
< 2 to 3 sec @ 260°C
SOIC−8
SOIC−8
SOIC−8
TSSOP−8
TSSOP−8
TSSOP−8
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
Continuous
Surge
V
I
≤
V
CC
V
I
≥V
EE
Condition 2
Rating
8 to 0
−8
to 0
6 to 0
−6
to 0
50
100
−40
to +85
−65
to +150
190
130
41 to 44
±5%
185
140
41 to 44
±5%
265
Units
V
V
V
mA
°C
°C
°C/W
°C/W
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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2
MC100LVEL01
Table 3. LVPECL DC CHARACTERISTICS
(V
CC
= 3.3 V; V
EE
= 0 V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
2215
1470
2135
1490
Min
Typ
15
2295
1605
Max
20
2420
1745
2420
1825
150
0.5
2275
1490
2135
1490
Min
25°C
Typ
15
2345
1595
Max
20
2420
1680
2420
1825
150
0.5
2275
1490
2135
1490
Min
85°C
Typ
17
2345
1595
Max
22
2420
1680
2420
1825
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−
2.0 V.
Table 4. LVNECL DC CHARACTERISTICS
(V
CC
= 0 V; V
EE
=
−3.3
V (Note 1))
−40°C
Symbol
I
EE
V
OH
V
OL
V
IH
V
IL
I
IH
I
IL
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
0.5
−1085
−1830
−1165
−1810
Min
Typ
15
−1005
−1695
Max
20
−880
−1555
−880
−1475
150
0.5
−1025
−1810
−1165
−1810
Min
25°C
Typ
15
−955
−1705
Max
20
−880
−1620
−880
−1475
150
0.5
−1025
−1810
−1165
−1810
Min
85°C
Typ
17
−955
−1705
Max
22
−880
−1620
−880
−1475
150
Unit
mA
mV
mV
mV
mV
mA
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary
±0.3
V.
2. Outputs are terminated through a 50
W
resistor to V
CC
−2
volts.
Table 5. AC CHARACTERISTICS
(V
CC
= 3.3 V; V
EE
= 0 V or V
CC
= 0 V; V
EE
=
−3.3
V (Note 1))
−40°C
Symbol
f
max
t
PLH
t
PHL
t
skew
t
JITTER
t
r
t
f
Characteristic
Maximum Toggle Frequency
Propagation Delay to Output
Within Device Skew
Cycle-to-Cycle Jitter
Output Rise/Fall Times Q (20%
−
80%)
120
210
Min
Typ
TBD
310
40
TBD
225
320
120
510
100
270
Max
Min
25°C
Typ
TBD
370
40
TBD
225
320
120
470
100
290
Max
Min
85°C
Typ
TBD
390
40
TBD
225
320
490
100
Max
Unit
GHz
ps
ps
ps
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. V
EE
can vary
±0.3
V.
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3
MC100LVEL01
Q
Driver
Device
Q
Z
o
= 50
W
50
W
50
W
D
Z
o
= 50
W
D
Receiver
Device
V
TT
V
TT
= V
CC
−
3.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note
AND8020/D
−
Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
ECL Clock Distribution Techniques
−
Designing with PECL (ECL at +5.0 V)
−
ECLinPSt I/O SPiCE Modeling Kit
−
Metastability and the ECLinPS Family
−
Interfacing Between LVDS and ECL
−
The ECL Translator Guide
−
Odd Number Counters Design
−
Marking and Date Codes
−
Termination of ECL Logic Devices
−
Interfacing with ECLinPS
−
AC Characteristics of ECL Devices
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MC100LVEL01
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AK
−X−
A
8
5
B
1
S
4
0.25 (0.010)
M
Y
M
−Y−
G
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
DIM
A
B
C
D
G
H
J
K
M
N
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
_
8
_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
_
8
_
0.010
0.020
0.228
0.244
C
−Z−
H
D
0.25 (0.010)
M
SEATING
PLANE
N
X 45
_
0.10 (0.004)
M
J
Z Y
S
X
S
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm
inches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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