Changes to Figure 23 and Figure 24............................................. 11
4/2016—Revision 0: Initial Version
Rev. A | Page 2 of 18
Data Sheet
SPECIFICATIONS
ADP1761
V
IN
= V
OUT
+ 0.2 V or V
IN
= 1.1 V, whichever is greater, I
LOAD
= 10 mA, C
IN
= 10 µF, C
OUT
= 10 µF, C
REF
= 1 µF, C
REG
= 1 µF, T
A
= 25°C,
Minimum and maximum limits at T
J
= −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
INPUT VOLTAGE SUPPLY RANGE
CURRENT
Operating Supply Current
Symbol
V
IN
I
GND
Test Conditions/Comments
T
J
= −40°C to +125°C
I
LOAD
= 0 µA
I
LOAD
= 10 mA
I
LOAD
= 100 mA
I
LOAD
= 1 A
EN = GND
T
J
= −40°C to +85°C,
V
IN
= (V
OUT
+ 0.2 V) to 1.98 V
T
J
= 85°C to 125°C,
V
IN
= (V
OUT
+ 0.2 V) to 1.98 V
10 Hz to 100 kHz, V
IN
= 1.1 V, V
OUT
= 0.9 V
100 Hz to 100 kHz, V
IN
= 1.1 V, V
OUT
= 0.9 V
10 Hz to 100 kHz, V
IN
= 1.5 V, V
OUT
= 1.3 V
100 Hz to 100 kHz, V
IN
= 1.5 V, V
OUT
= 1.3 V
10 Hz to 100 kHz, V
IN
= 1.7 V, V
OUT
= 1.5 V
100 Hz to 100 kHz, V
IN
= 1.7 V, V
OUT
= 1.5 V
V
OUT
= 0.9 V to 1.5 V, I
LOAD
= 100 mA
At 10 kHz
At 100 kHz
I
LOAD
= 1 A, modulated V
IN
10 kHz, V
OUT
= 1.3 V, V
IN
= 1.5 V
100 kHz, V
OUT
= 1.3 V, V
IN
= 1.5 V
1 MHz, V
OUT
= 1.3 V, V
IN
= 1.5 V
10 kHz, V
OUT
= 0.9 V, V
IN
= 1.1 V
100 kHz, V
OUT
= 0.9 V, V
IN
= 1.1 V
1 MHz, V
OUT
= 0.9 V, V
IN
= 1.1 V
T
A
= 25°C
V
OUT_FIXED
V
OUT_ADJ
V
OUT
0.9
0.5
−0.5
−1
−1.5
49.5
48.8
2.95
−0.15
0.25
12
30
0.6
10
2
50.0
50.0
3.0
1.5
1.5
+0.5
+1.5
+1.5
50.5
51.0
3.055
+0.15
0.44
23
53
12
2.4
%/V
%/A
mV
mV
ms
µA
A
V
V
%
%
%
µA
µA
Min
1.10
Typ
Max
1.98
8
8
8.5
11
180
800
12
2
15
2
21
2
4
3
67
51
41
66
50
35
Unit
V
mA
mA
mA
mA
µA
µA
µA
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
nV/√Hz
nV/√Hz
dB
dB
dB
dB
dB
dB
Shutdown Current
I
GND-SD
4.5
4.9
5.5
7.3
2
OUTPUT NOISE
1
OUT
NOISE
Noise Spectral Density
OUT
NSD
POWER SUPPLY REJECTION RATIO
1
PSRR
OUTPUT VOLTAGE
Output Voltage Range
Fixed Output Voltage Accuracy
ADJUSTABLE PIN CURRENT
ADJUSTABLE OUTPUT VOLTAGE GAIN FACTOR
REGULATION
Line Regulation
Load Regulation
2
DROPOUT VOLTAGE
3
START-UP TIME
1, 4
SOFT START CURRENT
CURRENT-LIMIT THRESHOLD
5
I
ADJ
A
D
I
LOAD
= 100 mA, T
A
= 25°C
10 mA < I
LOAD
< 1 A, V
IN
= (V
OUT
+ 0.2 V) to
1.98 V, T
J
= 0°C to 85°C
10 mA < I
LOAD
< 1 A, V
IN
= (V
OUT
+ 0.2 V) to
1.98 V
T
A
= 25°C
V
IN
= (V
OUT
+ 0.2 V) to 1.98 V
T
A
= 25°C
V
IN
= (V
OUT
+ 0.2 V) to 1.98 V
V
IN
= (V
OUT
+ 0.2 V) to 1.98 V
I
LOAD
= 10 mA to 1 A
I
LOAD
= 100 mA, V
OUT
= 1.2 V
I
LOAD
= 1 A, V
OUT
= 1.2 V
C
SS
= 10 nF, V
OUT
= 1.3 V
1.1 V ≤ V
IN
≤ 1.98 V
Rev. A | Page 3 of 18
∆V
OUT
/∆V
IN
∆V
OUT
/∆I
OUT
V
DROPOUT
T
START-UP
I
SS
I
LIMIT
8
1.5
ADP1761
Parameter
THERMAL SHUTDOWN
Threshold
Hysteresis
POWER-GOOD (PG) OUTPUT THRESHOLD
Output Voltage
Falling
Rising
PG OUTPUT
Output Voltage Low
Leakage Current
Delay
1
PRECISION EN INPUT
Logic Input
High
Low
Input Logic Hysteresis
Input Leakage Current
Input Delay Time
UNDERVOLTAGE LOCKOUT
Input Voltage
Rising
Falling
Hysteresis
1
2
Data Sheet
Symbol
TS
SD
TS
SD-HYS
Test Conditions/Comments
T
J
rising
Min
Typ
150
15
Max
Unit
°C
°C
PG
FALL
PG
RISE
PG
LOW
I
PG-LKG
PG
DELAY
1.1 V ≤ V
IN
≤ 1.98 V
1.1 V ≤ V
IN
≤ 1.98 V
1.1 V ≤ V
IN
≤ 1.98 V, I
PG
≤ 1 mA
1.1 V ≤ V
IN
≤ 1.98 V
EN
RISING
to PG
RISING
1.1 V ≤ V
IN
≤ 1.98 V
595
550
EN = V
IN
or GND
From EN rising from 0 V to V
IN
to 0.1 × V
OUT
−7.5
−5
0.35
1
%
%
V
µA
ms
0.01
0.75
EN
HIGH
EN
LOW
EN
HYS
I
EN-LKG
tI
EN-DLY
UVLO
UVLO
RISE
UVLO
FALL
UVLO
HYS
625
580
45
0.01
100
690
630
1
mV
mV
mV
µA
µs
T
J
= −40°C to +125°C
T
J
= −40°C to +125°C
0.87
1.01
0.93
90
1.06
V
V
mV
Guaranteed by design and characterization; not production tested.
Based on an endpoint calculation using 10 mA and 1 A loads.
3
Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage, which applies only for output
voltages above 1.1 V.
4
Start-up time is defined as the time from the rising edge of EN to VOUT being at 90% of the nominal value.
5
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 1.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 1.0 V, or 0.9 V.
INPUT AND OUTPUT CAPACITOR: RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
CAPACITANCE
1
Input
Output
Regulator
Reference
CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR)
C
IN
, C
OUT
C
REG
, C
REF
1
Symbol
C
IN
C
OUT
C
REG
C
REF
R
ESR
Test Conditions/Comments
T
A
= −40°C to +125°C
Min
7.0
7.0
0.7
0.7
Typ
10
10
1
1
Max
Unit
µF
µF
µF
µF
T
A
= −40°C to +125°C
0.001
0.001
0.5
0.2
Ω
Ω
The minimum input and output capacitance must be >7.0 µF over the full range of the operating conditions. Consider the full range of the operating conditions in the
application during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended. Y5V and Z5U
capacitors are not recommended for use with any LDO.
Rev. A | Page 4 of 18
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
VIN to GND
EN to GND
VOUT to GND
SENSE to GND
VREG to GND
REFCAP to GND
VADJ to GND
SS to GND
PG to GND
Storage Temperature Range
Operating Temperature Range
Operating Junction Temperature
Lead Temperature (Soldering, 10 sec)
Rating
−0.3 V to +2.16 V
−0.3 V to +3.96 V
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to VIN
−0.3 V to +3.96 V
−65°C to +150°C
−40°C to +125°C
125°C
300°C
ADP1761
The junction to ambient thermal resistance (θ
JA
) of the package
is based on modeling and a calculation using a 4-layer board.
The junction to ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θ
JA
can vary, depending on
PCB material, layout, and environmental conditions. The specified
values of θ
JA
are based on a 4-layer, 4 in × 3 in circuit board. For
details about board construction, refer to JEDEC JESD51-7.
Ψ
JB
is the junction to board thermal characterization parameter
with units of °C/W. Ψ
JB
of the package is based on modeling and
a calculation using a 4-layer board. The JEDEC JESD51-12
document,
Guidelines for Reporting and Using Package Thermal
Information,
states that thermal characterization parameters are
not the same as thermal resistances. Ψ
JB
measures the component
power flowing through multiple thermal paths rather than a single
path, as in thermal resistance (θ
JB
). Therefore, Ψ
JB
thermal paths
include convection from the top of the package as well as radiation
from the package, factors that make Ψ
JB
more useful in real-
world applications. The maximum junction temperature (T
J
) is
calculated from the board temperature (T
B
) and power dissipation
(P
D
), using the following formula:
T
J
=
T
B
+ (P
D
×
Ψ
JB
)
Refer to the JEDEC JESD51-8 and JESD51-12 documents for
more detailed information about Ψ
JB
.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply only individually, not in
combination. The
ADP1761
can be damaged when junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that the junction temperature is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature can need to be derated.
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The junction temper-
ature (T
J
) of the device is dependent on the ambient temperature
(T
A
), the power dissipation of the device (P
D
), and the junction to
ambient thermal resistance of the package (θ
JA
). T
J
is calculated
using the following formula:
T
J
=
T
A
+ (P
D
× θ
JA
)
THERMAL RESISTANCE
θ
JA
and Ψ
JB
are specified for the worst case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
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