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8732AY-01LFT

Description
Clock Generators & Support Products 10 LVPECL OUT BUFFER/DIVIDER
Categorylogic    logic   
File Size211KB,17 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
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8732AY-01LFT Overview

Clock Generators & Support Products 10 LVPECL OUT BUFFER/DIVIDER

8732AY-01LFT Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Lead free
Is it Rohs certified?conform to
MakerIDT (Integrated Device Technology)
Parts packaging codeTQFP
package instructionLQFP-52
Contacts52
Manufacturer packaging codePPG52
Reach Compliance Codecompliant
ECCN codeEAR99
Is SamacsysN
series8732
Input adjustmentDIFFERENTIAL MUX
JESD-30 codeS-PQFP-G52
JESD-609 codee3
length10 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level3
Number of functions1
Number of inverted outputs
Number of terminals52
Actual output times10
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP52,.47SQ
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.15 ns
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width10 mm
minfmax350 MHz
Base Number Matches1
Low Voltage, Low Skew
3.3V LVPECL Clock Generator
Data Sheet
8732-01
G
ENERAL
D
ESCRIPTION
The 8732-01 is a low voltage, low skew, 3.3V LVPECL Clock
Generator. The 8732-01 has two selectable clock inputs. The
CLK0, nCLK0 pair can accept most standard differential input
levels. The single ended clock input accepts LVCMOS or LVTTL
input levels. The 8732-01 has a fully integrated PLL along with
frequency configurable outputs. An external feedbackinput and
outputs regenerate clocks with “zero delay”.
The 8732-01 has multiple divide select pins for each bank of
outputs along with 3 independent feedback divide select pins
allowing the 8732-01 to function both as a frequency multiplier
and divider. The PLL_SEL input can be usedto bypass the
PLL for test and system debug purposes.In bypass mode,
the input clock is routed around the PLLand into the internal
output dividers.
Features
Ten differential 3.3V LVPECL outputs
Selectable differential CLK0, nCLK0 or
LVCMOS/LVTTL CLK1 inputs
CLK0, nCLK0 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
CLK1 accepts the following input levels:
LVCMOS or LVTTL
Maximum output frequency: 350MHz
VCO range: 250MHz to 700MHz
External feedback for “zero delay” clock regeneration
with configurable frequencies
Cycle-to-cycle jitter: CLK0, nCLK0, 50ps (maximum)
CLK1, 80ps (maximum)
Output skew: 150ps (maximum)
Static phase offset: -150ps to 150ps
Lead-Free package fully RoHS compliant
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
FBDIV_SEL2
FBDIV_SEL1
FBDIV_SEL0
nFB_IN
nQFB1
nQFB0
FB_IN
QFB1
QFB0
V
CCO
V
CCO
nQB3
38
35
34
QB2
V
EE
MR
V
CCO
31
nQA2
QA3
nQA3
V
EE
10
11
12
30
29
28
QB1
nQB0
QB0
V
EE
33
V
CC
V
EE
V
CCO
QA0
1
2
52 51 50 49 48 47 46 45 44 43 42 41 40
39
nQA1
V
EE
PLL_SEL
V
CCO
5
6
7
ICS8732-01
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
DIV_SELA1
DIV_SELA0
V
EE
nc
DIV_SELB1
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y package
Top View
©2016 Integrated Device Technology, Inc
1
Revision E January 22, 2016
DIV_SELB0
V
CC
nCLK0
CLK0
CLK1
CLK_SEL
V
CC
V
CCA
V
EE

8732AY-01LFT Related Products

8732AY-01LFT 8732AY-01LF
Description Clock Generators & Support Products 10 LVPECL OUT BUFFER/DIVIDER Clock Generators & Support Products 10 LVPECL OUT BUFFER/DIVIDER
Brand Name Integrated Device Technology Integrated Device Technology
Is it lead-free? Lead free Lead free
Is it Rohs certified? conform to conform to
Maker IDT (Integrated Device Technology) IDT (Integrated Device Technology)
Parts packaging code TQFP TQFP
package instruction LQFP-52 LQFP-52
Contacts 52 52
Manufacturer packaging code PPG52 PPG52
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Is Samacsys N N
series 8732 8732
Input adjustment DIFFERENTIAL MUX DIFFERENTIAL MUX
JESD-30 code S-PQFP-G52 S-PQFP-G52
JESD-609 code e3 e3
length 10 mm 10 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Humidity sensitivity level 3 3
Number of functions 1 1
Number of terminals 52 52
Actual output times 10 10
Maximum operating temperature 70 °C 70 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP
Encapsulate equivalent code QFP52,.47SQ QFP52,.47SQ
Package shape SQUARE SQUARE
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius) 260 260
power supply 3.3 V 3.3 V
Certification status Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.15 ns 0.15 ns
Maximum seat height 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V
surface mount YES YES
Temperature level COMMERCIAL COMMERCIAL
Terminal surface Matte Tin (Sn) - annealed Matte Tin (Sn) - annealed
Terminal form GULL WING GULL WING
Terminal pitch 0.65 mm 0.65 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
width 10 mm 10 mm
minfmax 350 MHz 350 MHz
Base Number Matches 1 1
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