This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found
on the last page.
HIGHLIGHTS
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Synchronization Management Unit (SMU) provides tools to man-
age physical layer and packet based synchronous clocks for IEEE
1588 / PTP Telecom Profile applications
Supports independent IEEE 1588 and Synchronous Ethernet
(SyncE) timing paths
Combo mode provides SyncE physical layer frequency support for
IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time
Slave Clocks (T-TSC) per G.8273.2
Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally
Controlled Oscillators (DCOs) for PTP clock synthesis
DCO frequency resolution is [(77760 / 1638400) * 2^-48] or
~1.686305041e-10 ppm
DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks
Two independent Time of Day (ToD) counters/time accumulators,
one associated with each of DPLL1 and DPLL2, can be used to
track differences between the two time domains and to time-stamp
external events
DPLL3 performs rate conversions to frequency synchronization
interfaces or for other general purpose timing applications
APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz
to 20 MHz) for: 1000BASE-T and 1000BASE-X
Fractional-N input dividers support a wide range of reference fre-
quencies
Locks to 1 Pulse Per Second (PPS) references
It can be configured from an external EEPROM after reset
Differential reference inputs (IN1 to IN4) accept clock frequencies
between 1 PPS and 650 MHz
Single ended inputs (IN5 to IN6) accept reference clock frequen-
cies between 1 PPS and 162.5 MHz
Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
Reference monitors qualify/disqualify references depending on
activity, frequency and LOS pins
Automatic reference selection state machines select the active ref-
erence for each DPLL based on the reference monitors, priority
tables, revertive and non-revertive settings and other programma-
ble settings
Fractional-N input dividers enable the DPLLs to lock to a wide
range of reference clock frequencies including: 10/100/1000 Ether-
Telcordia GR-253-CORE Stratum 3 Clock (S3) and SONET Mini-
mum Clock (SMC)
DESCRIPTION
The 82P33814 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE
1588 / Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths
that control: PTP clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with
Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to- input, input-to-output and output-to-
output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize lower-rate Ethernet interfaces; as
well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
The 82P33814 accepts four differential reference inputs and two single ended reference inputs that can operate at common GNSS, Ethernet,
SONET/SDH and PDH frequencies that range in frequency from 1 Pulse Per Second (PPS) to 650 MHz. The references are continually monitored for
loss of signal and for frequency offset per user programmed thresholds. All of the references are available to all three DPLLs. The active reference for
each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on
the reference monitors and LOS inputs.
The 82P33814 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 or DPLL2 can lock to the clock refer-
ence and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended refer-
ence inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync
signals can have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 or DPLL2 to phase align its frame sync and multi-frame
sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input.
DPLL1 and DPLL2 support four primary operating modes: Free-Run, Locked, Holdover and DCO. In Free-Run mode the DPLLs synthesize clocks
based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term
output frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses fre-
quency data acquired while in Locked mode to generate accurate frequencies when input references are not available. In DCO mode the DPLL con-
trol loop is opened and the DCO can be controlled by a PTP clock recovery servo running on an external processor to synthesize PTP clocks.
The 82P33814 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-
mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the
DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked and DCO modes.
When used with a suitable system clock, DPLL1 and DPLL2 meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise toler-
ance, transient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, ITU-
T G.8263, ITU-T G.8273.2, Telcordia GR-1244 Stratum 3 (S3), Telcordia GR-253-CORE Stratum 3 (S3) and SONET Minimum Clock (SMC).
DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be
used to lock the DPLL directly to a 1 PPS reference. The 69 mHz and the 92 mHz bandwidths can be used for G.8273.2. The 92 mHz bandwidth can
be used for G.8262/G.813 Option 2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used
for G.8262/G.813 Option 1 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.
DPLL1 and DPLL2 are each connected to Time of Day (ToD) counters or time accumulators; these ToD counters/time accumulators can be used
to track differences between the two time domains and to time-stamp external events by using reference inputs as triggers.
DPLL3 supports three primary operation modes: Free-Run, Locked and Holdover. DPLL3 is a wideband (BW > 25Hz) frequency translator that can
be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048 MHz synchronization interface clock.
In Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per ITU-T G.8275.2, DPLL1 and DPLL2 are both used;
one DPLL is configured as a DCO to synthesize PTP clocks and the other DPLL is configured as an EEC/SEC to generate physical layer clocks.
Combo mode provides physical layer frequency support from the EEC/SEC to the PTP clock.
In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, DPLL1 or DPLL2 can be configured as an EEC/SEC to output
clocks for the T0 reference point and DPLL3 can be used to output clocks for the T4 reference point.
Clocks generated by DPLL1 or DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The
output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.
All 82P33814 control and status registers are accessed through an I2C slave, SPI or the UART microprocessor interface. For configuring the
DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.
warning: creating .stack section with default size of 400 (hex) words.Use-stack option to change the default size.
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