Clock Generator for Cavium
Processors
Data Sheet
8413S08
General Description
The 8413S08 is a high performance PLL-based clock generator
optimized for processor core, PCI/PCI-X/PCIe bus, SGMII and
Gigabit Ethernet PHY clocks. The clock generator offers ultra-low
jitter outputs that make it ideal to serve as a central clocking device
for multiple clock destinations. The output frequencies are generated
from a 25MHz parallel resonant crystal, or external differential input
source. The industrial temperature range of the 8413S08 supports
tele-communication, networking and storage requirements.
Features
•
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Eight selectable 100MHz or 125MHz clocks for PCI Express and
sRIO, HCSL interface levels
One 156.25MHz SGMII clock, LVPECL interface levels
Three LVCMOS/LVTTL outputs, 20
output impedance
Selectable external crystal or differential (single-ended) input
source
Crystal oscillator interface designed for 25MHz, parallel resonant
crystal
Differential CLK, nCLK input pair that can accept: LVPECL, LVDS,
LVHSTL, HCSL input levels
Internal resistor bias on nCLK pin allows the user to drive CLK
input with external single-ended (LVCMOS/ LVTTL) input levels
Output supply voltage modes:
V
DD
/ V
DDO
3.3V/3.3V
3.3V/2.5V
Full 3.3V output supply mode (HCSL)
PCI Express™
(2.5 Gb/s), Gen 2 (5 Gb/s), and Gen 3 (8 Gb/s) jitter
compliant
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
QD
QC
V
DDO_CD
OE_QREF0
OE_CD
F_SELB
F_SELA
GND
nQB
QB
V
DDO_REF0
QREF0
GND
V
DDO_B
56 55 54 53 52 51 50 49 48 47 46 45 44 43
V
DDO_REF
QREF1
nQREF1
QREF2
nQREF2
QREF3
nQREF3
V
DDO_REF
V
DD
V
DDA
XTAL_IN
XTAL_OUT
nXTAL_SEL
GND
1
2
3
4
5
6
7
8
9
10
11
42
41
40
39
38
37
36
35
34
33
32
31
30
29
V
DD
IREF
V
DDO_A
nQA7
QA7
nQA6
QA6
V
DDO_A
nQA5
QA5
nQA4
QA4
V
DDO_A
GND
ICS8413S08I
56-Lead VFQFN
8mm x 8mm x 0.925mm
package body
K Package
Top View
12
13
14
15 16 17 18 19 20 21 22 23 24 25 26 27 28
nPLL_SEL
V
DDO_A
QA0
nQA0
QA1
nQA1
V
DDO_A
QA2
nQA2
QA3
nQA3
CLK
nCLK
V
DDO_A
©2016 Integrated Device Technology, Inc.
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8413S08 Data Sheet
Block Diagram
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
0 = 100MHz
1 = 125MHz
nPLL_SEL
nXTAL-SEL
Pulldown
Pulldown
nQA3
QA4
nQA4
QA5
nQA5
QA6
nQA6
QA7
XTAL_IN
25MHz
XTAL_OUT
Pulldown
PU/PD
nQA7
OSC
0
1
FemtoClock PLL
2.5GHz Center Frequency
0
1
0 = 156.25MHz
1 = 100MHz
QB
nQB
CLK
nCLK
50MHz
QC
33.3 MHz
OE_CD
FSEL_A
FSEL_B
Pulldown
Pulldown
Clock Output
Control Logic
OE_QREF0_
Pullup
Pullup
QD
QREF0
QREF1
nQREF1
QREF2
nQREF2
QREF3
nQREF3
©2016 Integrated Device Technology, Inc.
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8413S08 Data Sheet
Table 1. Pin Descriptions
Number
1, 8
2, 3
4, 5
6, 7
9, 42
10
11, 12
13
14, 29,
46, 54
15
16
17
18, 23, 28,
30, 35, 40
19, 20
21, 22
24, 25
26, 27
31, 32
33, 34
36, 37
38, 39
41
43
44, 45
47
48
49
50
Name
V
DDO_REF
QREF1,
nQREF1
QREF2,
nQREF2
QREF3,
nQREF3
V
DD
V
DDA
XTAL_IN,
XTAL_OUT
nXTAL_SEL
GND
nPLL_SEL
CLK
nCLK
V
DDO_A
QA0, nQA0
QA1, nQA1
QA2, nQA2
QA3, nQA3
QA4, nQA4
QA5, nQA5
QA6, nQA6
QA7, nQA7
I
REF
V
DDO_B
QB, nQB
F_SELA
F_SELB
OE_CD
OE_QREF0
Power
Output
Output
Output
Power
Power
Input
Input
Power
Input
Input
Input
Power
Output
Output
Output
Output
Output
Output
Output
Output
Input
Power
Output
Input
Input
Input
Input
Pulldown
Pulldown
Pullup
Pullup
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Type
Description
QREF[1:3], nQREF[1:3] (LVPECL) output supply pins. 3.3V or 2.5V supply.
Differential reference output pair. 3.3V or 2.5V LVPECL interface levels.
Differential reference output pair. 3.3V or 2.5V LVPECL interface levels.
Differential reference output pair. 3.3V or 2.5V LVPECL interface levels.
Core supply pins.
Analog supply pin.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input.
Input source control pin. See Table 3D. LVCMOS/LVTTL interface levels.
Power supply ground.
PLL bypass control pin. See Table 3C. LVCMOS/LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input. Internal resistor bias to V
DD
/2.
Bank A (HCSL) output supply pins. 3.3V supply.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
Differential output pair. HCSL interface levels.
External fixed precision resistor (475
) from this pin to ground provides a
reference current used for differential current-mode QAx, nQAx outputs.
Bank B (LVPECL) output supply pin. 3.3V or 2.5V supply.
Differential output pair. 3.3V or 2.5V LVPECL interface levels.
Selects the QAx, nQAx output frequency. See Table 3A.
LVCMOS/LVTTL interface levels.
Selects the QB output frequency. See Table 3B.
LVCMOS/LVTTL interface levels.
Active HIGH output enable for Bank C and Bank D outputs. See Table 3E.
LVCMOS/LVTTL interface levels.
Active HIGH output enable for QREF0 output. See Table 3F.
LVCMOS/LVTTL interface levels.
Pin Descriptions continues on next page.
©2016 Integrated Device Technology, Inc.
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8413S08 Data Sheet
Number
51
52
53
55
56
Name
V
DDO_CD
QC
QD
QREF0
V
DDO_REF0
Power
Output
Output
Output
Power
Type
Description
Bank C and D (LVCMOS) output supply pin. 3.3V or 2.5V supply.
Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
Single-ended output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
Single-ended reference output. 3.3V or 2.5V LVCMOS/LVTTL interface levels.
QREF0 (LVCMOS) output supply pin. 3.3V or 2.5V supply.
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
V
DD,
V
DDO_A,
V
DDO_B,
V
DDO_CD,
V
DDO_QREF0,
V
DDO_QREF
= 3.465V
V
DD
= 3.465V,
V
DDO_B,
V
DDO_CD,
V
DDO_QREF0
=
2.625V
Test Conditions
Minimum
Typical
2
4
Maximum
Units
pF
pF
C
PD
Power Dissipation Capacitance
(per output)
4
51
51
pF
k
k
R
PULLUP
R
PULLDOWN
Input Pullup Resistor
Input Pulldown Resistor
Output
Impedance
QC, QD,
QREF0
QC, QD,
QREF0
V
DDO_CD,
V
DDO_QREF0
= 3.465V
V
DDO_CD,
V
DDO_QREF0
= 2.625V
20
25
R
OUT
©2016 Integrated Device Technology, Inc.
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October 3, 2016
8413S08 Data Sheet
Function Tables
Table 3A. QAx, nQAx Control Input Function Table
Input
FSEL_A
0 (default)
1
Output Frequency
QAx, nQAx[0:7]
100MHz
125MHz
Table 3B. QB, nQB Control Input Function Table
Input
FSEL_B
0 (default)
1
Output Frequency
QB, nQB
156.25MHz
100MHz
Table 3C. nPLL_SEL Control Input Function Table
Input
nPLL_SEL
0 (default)
1
Operation
PLL Mode
PLL Bypass
Table 3D. nXTAL_SEL Control Input Function Table
Input
nXTAL_SEL
0 (default)
1
Clock Source
XTAL_IN, XTAL_OUT
CLK, nCLK
Table 3E. OE_CD Control Input Function Table
Input
OE_CD
0
1(default)
Outputs
QC, QD
High-Impedance
Enabled
able 3F. OE_QREF0 Control Input Function Table
Input
OE_QREF0
0
1(default)
Output
QREF0
High-Impedance
Enabled
©2016 Integrated Device Technology, Inc.
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October 3, 2016
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