Intel
®
I/O Controller Hub 6 (ICH6)
Family
Datasheet
For the Intel
®
82801FB ICH6, 82801FR ICH6R and 82801FBM ICH6-M
I/O Controller Hubs
January 2005
Document Number: 301473-002
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®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
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future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
82801FB ICH6, Intel
®
82801FR ICH6R, and Intel
®
82801FBM ICH6-M components may contain design defects or errors known as errata
which may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I
2
C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I
2
C bus/protocol and was developed by Intel.
Implementations of the I
2
C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Intel, Intel SpeedStep and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other
countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004-2005, Intel Corporation
2
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Contents
Contents
1
2
Introduction
............................................................................................................................. 43
1.2
Overview .............................................................................................................................46
Signal Description
................................................................................................................. 53
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
2.21
2.22
Direct Media Interface (DMI) to Host Controller.................................................................. 56
PCI Express* ......................................................................................................................56
Link to LAN Connect ........................................................................................................... 57
EEPROM Interface ............................................................................................................. 57
Firmware Hub Interface ...................................................................................................... 57
PCI Interface ....................................................................................................................... 58
Serial ATA Interface............................................................................................................60
IDE Interface ....................................................................................................................... 61
LPC Interface ...................................................................................................................... 62
Interrupt Interface ............................................................................................................... 63
USB Interface ..................................................................................................................... 64
Power Management Interface.............................................................................................65
Processor Interface............................................................................................................. 67
SMBus Interface ................................................................................................................. 68
System Management Interface ........................................................................................... 68
Real Time Clock Interface ..................................................................................................69
Other Clocks ....................................................................................................................... 69
Miscellaneous Signals ........................................................................................................ 69
AC ’97/Intel
®
High Definition Audio Link ............................................................................. 70
General Purpose I/O ...........................................................................................................71
Power and Ground.............................................................................................................. 73
Pin Straps ........................................................................................................................... 74
2.22.1 Functional Straps ................................................................................................... 74
2.22.2 External RTC Circuitry ........................................................................................... 76
2.22.3 Power Sequencing Requirements ......................................................................... 76
2.22.3.1 V5REF / Vcc3_3 Sequencing Requirements ......................................... 76
2.22.3.2 3.3 V/1.5 V Standby Power Sequencing Requirements ........................ 76
2.22.3.3 3.3 V/2.5 V Power Sequencing Requirements....................................... 77
2.22.3.4 Vcc1_5/V_Processor_IO Power Sequencing Requirements .................77
3
Pin States
.................................................................................................................................. 79
3.1
3.2
3.3
3.4
Integrated Pull-Ups and Pull-Downs ................................................................................... 79
IDE Integrated Series Termination Resistors ..................................................................... 80
Output and I/O Signals Planes and States ......................................................................... 80
Power Planes for Input Signals........................................................................................... 89
4
5
System Clock Domains
.......................................................................................................95
Functional Description
........................................................................................................ 97
5.1
PCI-to-PCI Bridge (D30:F0) ................................................................................................ 97
5.1.1 PCI Bus Interface................................................................................................... 97
5.1.2 PCI Bridge As an Initiator ...................................................................................... 97
5.1.2.1 Memory Reads and Writes .................................................................... 98
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
3
Contents
5.2
5.3
5.4
5.5
5.1.2.2 I/O Reads and Writes............................................................................. 98
5.1.2.3 Configuration Reads and Writes ............................................................ 98
5.1.2.4 Locked Cycles........................................................................................ 98
5.1.2.5 Target / Master Aborts ........................................................................... 98
5.1.2.6 Secondary Master Latency Timer .......................................................... 98
5.1.2.7 Dual Address Cycle (DAC) .................................................................... 98
5.1.2.8 Memory and I/O Decode to PCI............................................................. 99
5.1.3 Parity Error Detection and Generation................................................................... 99
5.1.4 PCIRST#.............................................................................................................. 100
5.1.5 Peer Cycles ......................................................................................................... 100
5.1.6 PCI-to-PCI Bridge Model ..................................................................................... 100
5.1.7 IDSEL to Device Number Mapping...................................................................... 100
5.1.8 Standard PCI Bus Configuration Mechanism ...................................................... 100
PCI Express* Root Ports (D28:F0,F1,F2,F3).................................................................... 101
5.2.1 Interrupt Generation............................................................................................. 101
5.2.2 Power Management............................................................................................. 102
5.2.2.1 S3/S4/S5 Support ................................................................................ 102
5.2.2.2 Resuming from Suspended State ........................................................ 102
5.2.2.3 Device Initiated PM_PME Message..................................................... 102
5.2.2.4 SMI/SCI Generation............................................................................. 103
5.2.3 SERR# Generation .............................................................................................. 103
5.2.4 Hot-Plug ............................................................................................................... 103
5.2.4.1 Presence Detection.............................................................................. 103
5.2.4.2 Message Generation............................................................................ 104
5.2.4.3 Attention Button Detection ................................................................... 104
5.2.4.4 SMI/SCI Generation............................................................................. 105
LAN Controller (B1:D8:F0)................................................................................................ 105
5.3.1 LAN Controller PCI Bus Interface ........................................................................ 106
5.3.1.1 Bus Slave Operation ............................................................................ 106
5.3.1.2 CLKRUN# Signal (Mobile Only)........................................................... 107
5.3.1.3 PCI Power Management...................................................................... 107
5.3.1.4 PCI Reset Signal.................................................................................. 108
5.3.1.5 Wake-Up Events .................................................................................. 108
5.3.1.6 Wake on LAN* (Preboot Wake-Up) ..................................................... 109
5.3.2 Serial EEPROM Interface .................................................................................... 109
5.3.3 CSMA/CD Unit..................................................................................................... 110
5.3.3.1 Full Duplex ........................................................................................... 110
5.3.3.2 Flow Control......................................................................................... 111
5.3.3.3 VLAN Support ...................................................................................... 111
5.3.4 Media Management Interface .............................................................................. 111
5.3.5 TCO Functionality ................................................................................................ 111
5.3.5.1 Advanced TCO Mode .......................................................................... 111
Alert Standard Format (ASF) ............................................................................................ 113
5.4.1 ASF Management Solution Features/Capabilities ............................................... 114
5.4.2 ASF Hardware Support........................................................................................ 115
5.4.2.1 82562EM/EX........................................................................................ 115
5.4.2.2 EEPROM (256x16, 1 MHz).................................................................. 115
5.4.2.3 Legacy Sensor SMBus Devices........................................................... 115
5.4.2.4 Remote Control SMBus Devices ......................................................... 115
5.4.2.5 ASF Sensor SMBus Devices ............................................................... 115
5.4.3 ASF Software Support ......................................................................................... 115
LPC Bridge (w/ System and Management Functions) (D31:F0)....................................... 116
4
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
Contents
5.6
5.7
5.8
5.9
LPC Interface ....................................................................................................... 116
5.5.1.1 LPC Cycle Types ................................................................................. 117
5.5.1.2 Start Field Definition............................................................................. 117
5.5.1.3 Cycle Type / Direction (CYCTYPE + DIR) ...........................................118
5.5.1.4 SIZE .....................................................................................................118
5.5.1.5 SYNC ...................................................................................................119
5.5.1.6 SYNC Time-Out ...................................................................................119
5.5.1.7 SYNC Error Indication.......................................................................... 119
5.5.1.8 LFRAME# Usage ................................................................................. 119
5.5.1.9 I/O Cycles ............................................................................................120
5.5.1.10 Bus Master Cycles ............................................................................... 120
5.5.1.11 LPC Power Management ..................................................................... 120
5.5.1.12 Configuration and Intel
®
ICH6 Implications.......................................... 120
DMA Operation (D31:F0) .................................................................................................. 121
5.6.1 Channel Priority ................................................................................................... 122
5.6.1.1 Fixed Priority ........................................................................................ 122
5.6.1.2 Rotating Priority ................................................................................... 122
5.6.2 Address Compatibility Mode ................................................................................ 122
5.6.3 Summary of DMA Transfer Sizes ........................................................................ 123
5.6.3.1 Address Shifting When Programmed for 16-Bit
I/O Count by Words ............................................................................. 123
5.6.4 Autoinitialize.........................................................................................................123
5.6.5 Software Commands ........................................................................................... 124
LPC DMA .......................................................................................................................... 124
5.7.1 Asserting DMA Requests..................................................................................... 124
5.7.2 Abandoning DMA Requests ................................................................................125
5.7.3 General Flow of DMA Transfers ..........................................................................125
5.7.4 Terminal Count .................................................................................................... 126
5.7.5 Verify Mode..........................................................................................................126
5.7.6 DMA Request De-assertion ................................................................................. 126
5.7.7 SYNC Field / LDRQ# Rules ................................................................................. 127
8254 Timers (D31:F0)....................................................................................................... 128
5.8.1 Timer Programming ............................................................................................. 128
5.8.2 Reading from the Interval Timer ..........................................................................129
5.8.2.1 Simple Read ........................................................................................ 130
5.8.2.2 Counter Latch Command .....................................................................130
5.8.2.3 Read Back Command .......................................................................... 130
8259 Interrupt Controllers (PIC) (D31:F0) ........................................................................131
5.9.1 Interrupt Handling ................................................................................................ 132
5.9.1.1 Generating Interrupts ...........................................................................132
5.9.1.2 Acknowledging Interrupts..................................................................... 132
5.9.1.3 Hardware/Software Interrupt Sequence...............................................133
5.9.2 Initialization Command Words (ICWx) ................................................................. 133
5.9.2.1 ICW1 .................................................................................................... 133
5.9.2.2 ICW2 .................................................................................................... 134
5.9.2.3 ICW3 .................................................................................................... 134
5.9.2.4 ICW4 .................................................................................................... 134
5.9.3 Operation Command Words (OCW) ....................................................................134
5.9.4 Modes of Operation ............................................................................................. 134
5.9.4.1 Fully Nested Mode ............................................................................... 134
5.9.4.2 Special Fully-Nested Mode ..................................................................135
5.9.4.3 Automatic Rotation Mode (Equal Priority Devices) ..............................135
5.5.1
Intel
®
I/O Controller Hub 6 (ICH6) Family Datasheet
5
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