Changes to Product Title ................................................................. 1
Changes to Ordering Guide .......................................................... 23
3/06—Rev. A to Rev. B
Changes to Table 2.............................................................................3
Updates to Outline Dimensions ................................................... 22
Changes to Ordering Guide .......................................................... 23
8/05—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 22
6/05—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
SPECIFICATIONS
AD5602/AD5612/AD5622
V
DD
= 2.7 V to 5.5 V, R
L
= 2 kΩ to GND, C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE
Resolution
AD5602
AD5612
AD5622
Relative Accuracy
2
AD5602
AD5612
AD5622
Differential Nonlinearity
2
Zero Code Error
Offset Error
Full-Scale Error
Gain Error
Zero Code Error Drift
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Capacitive Load Stability
Output Noise Spectral Density
Noise
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DC Output Impedance
Short Circuit Current
LOGIC INPUTS (SDA, SCL)
I
IN
, Input Current
V
INL
, Input Low Voltage
V
INH
, Input High Voltage
C
IN
, Pin Capacitance
V
HYST
, Input Hysteresis
LOGIC OUTPUTS (OPEN DRAIN)
V
OL
, Output Low Voltage
Floating-State Leakage Current
Floating-State Output Capacitance
Min
A, B, W, Y Versions
1
Typ
Max
Unit
Bits
8
10
12
±0.5
±0.5
±4
±2
±6
±1
10
±10
±0.037
LSB
LSB
LSB
LSB
LSB
LSB
mV
mV
mV
% of FSR
µV/°C
ppm of FSR/°C
V
µs
V/µs
pF
pF
nV/Hz
B, Y versions
B, Y versions
A version
B, Y versions
A, W versions
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
Test Conditions/Comments
DAC output unloaded
0.5
±0.063
0.5
±0.0004
5
2
0
6
0.5
470
1000
120
2
5
0.2
0.5
15
V
DD
10
Code ¼ to ¾
R
L
= ∞
R
L
= 2 kΩ
DAC code = midscale, 10 kHz
DAC code = midscale, 0.1 Hz to 10 Hz
bandwidth
1 LSB change around major carry
nV-sec
nV-sec
Ω
mA
±1
0.3 × V
DD
µA
V
V
pF
V
V
V
µA
pF
V
DD
= 3 V/5 V
0.7 × V
DD
2
0.1 × V
DD
0.4
0.6
±1
2
I
SINK
= 3 mA
I
SINK
= 6 mA
Rev. D | Page 3 of 24
AD5602/AD5612/AD5622
Parameter
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
I
DD
(All Power-Down Modes)
V
DD
= 4.5 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
POWER EFFICIENCY
I
OUT
/I
DD
1
2
Data Sheet
Min
2.7
75
60
0.3
0.15
96
A, B, W, Y Versions
1
Typ
Max
5.5
100
90
1
1
Unit
V
µA
µA
µA
µA
%
DAC active and excluding load current
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
I
LOAD
= 2 mA, V
DD
= 5 V
Test Conditions/Comments
Temperature ranges for A, B versions:
−40°C
to +125°C, typical at 25°C.
Linearity calculated using a reduced code range 64 to 4032.
3
Guaranteed by design and characterization, not production tested.
I
2
C TIMING SPECIFICATIONS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, f
SCL
= 3.4 MHz, unless otherwise noted.
1
Table 3.
Parameter
f
SCL 3
Test Conditions/Comments
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
2
t
1
t
2
t
3
t
4
t
5
t
6
t
7
Limit at T
MIN
, T
MAX
Min
Max
100
400
3.4
1.7
4
0.6
60
120
4.7
1.3
160
320
250
100
10
0
3.45
0
0.9
0
70
0
150
4.7
0.6
160
4
0.6
160
4.7
1.3
Unit
KHz
KHz
MHz
MHz
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
µs
ns
µs
µs
ns
µs
µs
Description
Serial clock frequency
t
HIGH
, SCL high time
t
LOW
, SCL low time
t
SU;DAT
, data setup time
t
HD;DAT
, data hold time
t
SU;STA
, setup time for a repeated start condition
t
HD;STA
, hold time (repeated) start condition
t
BUF
, bus free time between a stop and a start
condition
Fast mode
Rev. D | Page 4 of 24
Data Sheet
Parameter
t
8
Test Conditions/Comments
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
2
AD5602/AD5612/AD5622
Limit at T
MIN
, T
MAX
Min
Max
4
0.6
160
1000
300
10
80
20
160
300
300
10
80
20
160
1000
300
10
40
20
80
1000
300
80
160
300
300
40
80
50
10
Unit
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
t
SU;STO
, setup time for a stop condition
t
9
t
RDA
, rise time of SDA signal
t
10
t
FDA
, fall time of SDA signal
t
11
t
RCL
, rise time of SCL signal
t
11A
t
RCL1
, rise time of SCL signal after a repeated start
condition and after an acknowledge bit
t
12
t
SP 4
1
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Standard mode
Fast mode
High speed mode, C
B
= 100 pF
High speed mode, C
B
= 400 pF
Fast mode
High speed mode
10
20
t
FCL
, fall time of SCL signal
10
20
0
0
Pulse width of spike suppressed
See Figure 2. High speed mode timing specification applies to the
AD5602-1/AD5612-1/AD5622-1
only. Standard and fast mode timing specifications apply to the
AD5602-1/AD5612-1/AD5622-1
and
AD5602-2/AD5612-2/AD5622-2.
2
C
B
refers to the capacitance on the bus line.
3
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the device.
4
Input filtering on the SCL and SDA inputs suppress noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
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