Freescale Semiconductor
Technical Data
DSP56311
Rev. 8, 2/2005
DSP56311
24-Bit Digital Signal Processor
3
16
6
6
Memory Expansion Area
Program
RAM
32 K
×
24 bits
or
31 K
×
24 bits
and
Instruction
Cache
1024
×
24 bits
PM_EB
SCI
Triple
Timer
HI08
ESSI
EFCOP
X Data
RAM
48 K
×
24 bits
Y Data
RAM
48 K
×
24 bits
PIO_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data
Bus
Switch
Power
Management
JTAG
OnCE™
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
13
Control
The DSP56311 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
Internal
Data
Bus
Switch
24
Data
What’s New?
Rev. 8 includes the following
changes:
•
Adds lead-free packaging and
part numbers.
Clock
PLL
Generator
EXTAL
XTAL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
Data ALU
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
DE
PCAP
Figure 1.
DSP56311 Block Diagram
The Freescale DSP56311, a member of the DSP56300 DSP family, supports network applications with general filtering
operations. The Enhanced Filter Coprocessor (EFCOP) executes filter algorithms in parallel with core operations enhancing
signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance.
Like the other DSP56300 family members, the DSP56311 uses a high-performance, single-clock-cycle-per- instruction engine
(DSP56000 code-compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA)
controller (see
Figure 1).
The DSP56311 performs at up to 150 million multiply-accumulates per second (MMACS), attaining
up to 300 MMACS when the EFCOP is in use. It operates with an internal 150 MHz clock with a 1.8 volt core and
independent 3.3 volt input/output (I/O) power.
© Freescale Semiconductor, Inc., 1999, 2005. All rights reserved.
Table of Contents
Data Sheet Conventions .......................................................................................................................................ii
Features...............................................................................................................................................................iii
Target Applications ............................................................................................................................................. iv
Product Documentation ......................................................................................................................................iv
Chapter 1
Signals/Connections
1.1
1.2
1.3
1.5
1.6
1.7
1.8
1.9
1.10
1.11
1.12
Power ................................................................................................................................................................1-3
Ground ..............................................................................................................................................................1-3
Clock.................................................................................................................................................................1-3
External Memory Expansion Port (Port A) ......................................................................................................1-4
Interrupt and Mode Control ..............................................................................................................................1-7
Host Interface (HI08)........................................................................................................................................1-8
Enhanced Synchronous Serial Interface 0 (ESSI0) ........................................................................................1-11
Enhanced Synchronous Serial Interface 1 (ESSI1) ........................................................................................1-12
Serial Communication Interface (SCI) ...........................................................................................................1-13
Timers .............................................................................................................................................................1-14
JTAG and OnCE Interface ..............................................................................................................................1-15
Maximum Ratings.............................................................................................................................................2-1
Thermal Characteristics ....................................................................................................................................2-2
DC Electrical Characteristics............................................................................................................................2-3
AC Electrical Characteristics............................................................................................................................2-4
Package Description .........................................................................................................................................3-2
MAP-BGA Package Mechanical Drawing .....................................................................................................3-10
Thermal Design Considerations........................................................................................................................4-1
Electrical Design Considerations......................................................................................................................4-2
Power Consumption Considerations.................................................................................................................4-3
PLL Performance Issues ...................................................................................................................................4-4
Input (EXTAL) Jitter Requirements .................................................................................................................4-6
Chapter 2
Specifications
2.1
2.2
2.3
2.4
Chapter 3
Packaging
3.1
3.2
Chapter 4
Design Considerations
4.1
4.2
4.3
4.4
4.5
Appendix A
Power Consumption Benchmark
Data Sheet Conventions
OVERBAR
“asserted”
“deasserted”
Examples:
Indicates a signal that is active when pulled low (For example, the
RESET
pin is active when
low.)
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
Signal/Symbol
Logic State
Voltage
V
IL
/V
OL
V
IH
/V
OH
V
IH
/V
OH
V
IL
/V
OL
Signal State
PIN
True
Asserted
PIN
False
Deasserted
PIN
True
Asserted
PIN
False
Deasserted
Note:
Values for
V
IL
,
V
OL
,
V
IH
, and
V
OH
are defined by individual product specifications.
DSP56311 Technical Data, Rev. 8
ii
Freescale Semiconductor
Features
Table 1
lists the features of the DSP56311 device.
Table 1.
DSP56311 Features
Feature
Description
• Up to 150 million multiply-accumulates per second (MMACS) (300 MMACS using the EFCOP in filtering
applications) with a 150 MHz clock at 1.8 V core and 3.3 V I/O
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data arithmetic logic unit (Data ALU) with fully pipelined 24
×
24-bit parallel Multiplier-Accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
• Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
• Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
• Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
• Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
• Internal 24
×
24-bit filtering and echo-cancellation coprocessor that runs in parallel to the DSP core
• Operation at the same frequency as the core (up to 150 MHz)
• Support for a variety of filter modes, some of which are optimized for cellular base station applications:
• Real finite impulse response (FIR) with real taps
• Complex FIR with complex taps
• Complex FIR generating pure real or pure imaginary outputs alternately
• A 4-bit decimation factor in FIR filters, thus providing a decimation ratio up to 16
• Direct form 1 (DFI) Infinite Impulse Response (IIR) filter
• Direct form 2 (DFII) IIR filter
• Four scaling factors (1, 4, 8, 16) for IIR output
• Adaptive FIR filter with true least mean square (LMS) coefficient updates
• Adaptive FIR filter with delayed LMS coefficient updates
• Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to 34 programmable general-purpose input/output (GPIO) pins, depending on which peripherals are
enabled
• 192
×
24-bit bootstrap ROM
• 128 K
×
24-bit RAM total
• Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
Program
RAM Size
32 K
×
24-bit
31 K
×
24-bit
96 K
×
24-bit
Instruction
Cache Size
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
0
1024
×
24-bit
X Data RAM
Size*
48 K
×
24-bit
48 K
×
24-bit
16 K
×
24-bit
16 K
×
24-bit
24 K
×
24-bit
24 K
×
24-bit
32 K
×
24-bit
32 K
×
24-bit
40 K
×
24-bit
40 K
×
24-bit
Y Data RAM
Size*
48 K
×
24-bit
48 K
×
24-bit
16 K
×
24-bit
16 K
×
24-bit
24 K
×
24-bit
24 K
×
24-bit
32 K
×
24-bit
32 K
×
24-bit
40 K
×
24-bit
40 K
×
24-bit
Instruction
Cache
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
disabled
enabled
Switch
Mode
disabled
disabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
MSW1 MSW0
0/1
0/1
0
0
0
0
1
1
1
1
0/1
0/1
0
0
1
1
0
0
1
1
High-Performance
DSP56300 Core
Enhanced Filter
Coprocessor (EFCOP)
Internal Peripherals
:
Internal Memories
95 K
×
24-bit
80 K
×
24-bit
79 K
×
24-bit
64 K
×
24-bit
63 K
×
24-bit
48 K
×
24-bit
47 K
×
24-bit
*Includes 10 K
×
24-bit shared memory (that is, memory shared by the core and the EFCOP)
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
iii
Table 1.
DSP56311 Features (Continued)
Feature
Description
• Data memory expansion to two 256 K
×
24-bit word memory spaces using the standard external address
lines
• Program memory expansion to one 256 K
×
24-bit words memory space using the standard external
address lines
• External memory expansion port
• Chip select logic for glueless interface to static random access memory (SRAMs)
• Internal DRAM controller for glueless interface to dynamic random access memory (DRAMs) up to 100
MHz operating frequency
•
•
•
•
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
External Memory
Expansion
Power Dissipation
Packaging
• Molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions.
Target Applications
DSP56311 applications require high performance, low power, small packaging, and a large amount of internal
memory. The EFCOP can accelerate general filtering applications. Examples include:
•
•
•
•
•
Wireless and wireline infrastructure applications
Multi-channel wireless local loop systems
DSP resource boards
High-speed modem banks
IP telephony
Product Documentation
The documents listed in
Table 2
are required for a complete description of the DSP56311 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2.
DSP56311 Documentation
Name
DSP56311
User’s Manual
Description
Detailed functional description of the DSP56311 memory configuration,
operation, and register programming
Order Number
DSP56311UM
DSP56300FM
See the DSP56311 product website
DSP56300 Family
Detailed description of the DSP56300 family processor core and instruction set
Manual
Application Notes
Documents describing specific applications or optimized device operation
including code examples
DSP56311 Technical Data, Rev. 8
iv
Freescale Semiconductor
Signals/Connections
1
The DSP56311 input and output signals are organized into functional groups as shown in
Table 1-1. Figure 1-1
diagrams the DSP56311 signals by functional group. The remainder of this chapter describes the signal pins in
each functional group.
Table 1-1.
DSP56311 Functional Signal Groupings
Number of
Signals
20
66
2
3
18
Port A
1
24
13
5
Port B
2
Ports C and D
3
Port E
4
16
12
3
3
6
Functional Group
Power (V
CC
)
Ground (GND)
Clock
PLL
Address bus
Data bus
Bus control
Interrupt and mode control
Host interface (HI08)
Enhanced synchronous serial interface (ESSI)
Serial communication interface (SCI)
Timer
OnCE/JTAG Port
Notes:
1.
2.
3.
4.
5.
Port A signals define the external memory interface port, including the external address bus, data bus, and control signals.
Port B signals are the HI08 port signals multiplexed with the GPIO signals.
Port C and D signals are the two ESSI port signals multiplexed with the GPIO signals.
Port E signals are the SCI port signals multiplexed with the GPIO signals.
There are 5 signal connections that are not used. These are designated as no connect (NC) in the package description (see
Chapter 3).
Note:
The Clock Output (
CLKOUT
),
BCLK
,
BCLK
,
CAS
, and
RAS[0–3]
signals used by other DSP56300 family members
are supported by the DSP56311 at operating frequencies up to 100 MHz. Therefore, above 100 MHz, you must
enable bus arbitration by setting the Asynchronous Bus Arbitration Enable Bit (ABE) in the operating mode register.
When set, the ABE bit eliminates the required set-up and hold times for
BB
and
BG
with respect to
CLKOUT
. In
addition, DRAM access is not supported above 100 MHz.
DSP56311 Technical Data, Rev. 8
Freescale Semiconductor
1-1
京公网安备 11010802033920号
EEWORLD
