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5962-9161704MYA

Description
SRAM DUAL PORT STAT RAM 8KX16
Categorystorage    storage   
File Size216KB,23 Pages
ManufacturerIDT (Integrated Device Technology)
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5962-9161704MYA Overview

SRAM DUAL PORT STAT RAM 8KX16

5962-9161704MYA Parametric

Parameter NameAttribute value
Brand NameIntegrated Device Technology
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeFPACK
package instructionDFP, QFL84,1.2SQ
Contacts84
Manufacturer packaging codeFP84
Reach Compliance Codenot_compliant
ECCN code3A001.A.2.C
Maximum access time55 ns
Other featuresINTERRUPT FLAG; ARBITER; SEMAPHORE
I/O typeCOMMON
JESD-30 codeS-XQFP-F84
JESD-609 codee0
length29.21 mm
memory density131072 bit
Memory IC TypeDUAL-PORT SRAM
memory width16
Humidity sensitivity level1
Number of functions1
Number of ports2
Number of terminals84
word count8192 words
character code8000
Operating modeASYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize8KX16
Output characteristics3-STATE
ExportableYES
Package body materialUNSPECIFIED
encapsulated codeDFP
Encapsulate equivalent codeQFL84,1.2SQ
Package shapeSQUARE
Package formFLATPACK
Parallel/SerialPARALLEL
Peak Reflow Temperature (Celsius)240
power supply5 V
Certification statusQualified
Filter levelMIL-STD-883
Maximum seat height3.56 mm
Maximum standby current0.004 A
Minimum standby current2 V
Maximum slew rate0.335 mA
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal surfaceTIN LEAD
Terminal formFLAT
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width29.21 mm
HIGH-SPEED
8K x 16 DUAL-PORT
STATIC RAM
Features
IDT7025S/L
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Military: 20/25/35/55/70ns (max.)
– Industrial: 55ns (max.)
– Commercial: 15/17/20/25/35/55ns (max.)
Low-power operation
– IDT7025S
Active: 750mW (typ.)
Standby: 5mW (typ.)
– IDT7025L
Active: 750mW (typ.)
Standby: 1mW (typ.)
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
IDT7025 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = H for
BUSY
output flag on Master
M/S = L for
BUSY
input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 5V (±10%) power supply
Available in 84-pin PGA, Flatpack, PLCC, and 100-pin Thin
Quad Flatpack
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
R/W
L
UB
L
R/W
R
UB
R
LB
L
CE
L
OE
L
LB
R
CE
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
BUSY
L
A
12L
A
0L
(1,2)
I/O
8R
-I/O
15R
I/O
Control
I/O
Control
I/O
0R
-I/O
7R
BUSY
R
A
12R
A
0R
(1,2)
Address
Decoder
13
MEMORY
ARRAY
13
Address
Decoder
CE
L
OE
L
R/W
L
SEM
L
(2)
INT
L
NOTES:
1. (MASTER):
BUSY
is output; (SLAVE):
BUSY
is input.
2.
BUSY
outputs and
INT
outputs are non-tri-stated push-pull.
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
R
OE
R
R/W
R
SEM
R
INT
R
(2)
2683 drw 01
M/S
MARCH 2018
1
DSC 2683/12
©2018 Integrated Device Technology, Inc.
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