DS1371
I
2
C, 32-Bit Binary Counter
Watchdog Clock
www.maxim-ic.com
General Description
The DS1371 is a 32-bit binary counter that is
designed to continuously count time in seconds.
An additional counter that can generate a
periodic alarm or serve as a watchdog timer is
also provided. If enabled as a watchdog timer,
the watchdog strobe input pin provides a
hardware reset of the counter. If disabled, this
counter can be used as 3 Bytes of general-
purpose RAM. A configurable output can be
used as an interrupt or provide a square wave at
one of four selectable frequencies. The device is
programmed serially through a I
2
C bidirectional
bus.
Features
32-Bit Binary Counter
24-Bit Binary Counter Provides Periodic
Alarm, Watchdog Timer, or RAM
Strobe Input to Reset Watchdog Timer
Single Output Configurable as Interrupt or
Square Wave
I
2
C Serial Interface
Low-Voltage Operation
Operating Temperature Range:
-40°C to +85°C
Available in 8-Pin
μSOP
Ordering Information
PART
DS1371U
DS1371U+
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-
PACKAGE
8
μSOP
8
μSOP
TOP
MARK
1371
1371
Applications
Servers
Point-of-Sale Equipment
Portable Instruments
Elapsed Time Measurements
+
Denotes a lead-free/RoHS-compliant package. A + appears on the top
mark for lead-free packages.
Typical Operating Circuit
Pin Configuration
TOP VIEW
X1
X2
WDS
GND
1
2
3
4
8
7
6
5
V
CC
SQW/INT
SCL
SDA
DS1371
μSOP
1 of 15
REV: 070607
DS1371
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
CC
Pin Relative to Ground………………………………………………………..-0.3V to +6.0V
Voltage Range on SDA, SCL, and WDS Relative to Ground…………………………………..-0.3V to (V
CC
+0.5V)
Operating Temperature Range (noncondensing)……………………………………………………...-40°C to +85°C
Storage Temperature Range………………………………………………………………………….-55°C to +125°C
Soldering Temperature…………………………………………………………………...See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= -40°C to +85°C)
PARAMETER
Supply Voltage (Note 1)
Input Logic 1 (Notes 2, 3)
Input Logic 0 (Notes 2, 3)
SYMBOL
V
CC
V
IH
V
IL
MIN
1.7
0.7 V
CC
-0.3
TYP
3.3
MAX
5.5
V
CC
+ 0.3
0.3V
CC
UNITS
V
V
V
DC ELECTRICAL CHARACTERISTICS
(V
CC
= 1.7V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 4)
PARAMETER
Supply Voltage (Note 1)
Oscillator Operating Voltage
Range (Note 1)
Input Leakage
I/O Leakage
SDA Logic 0 Output (Note 1)
SYMBOL
V
CC
V
OSC
I
LI
I
LO
I
OLSDA
CONDITIONS
MIN
1.7
1.3
TYP
MAX
5.5
5.5
1
1
3
3.0
3.0
250
UNITS
V
V
μA
μA
mA
(Note 2)
(Note 3)
V
CC
> 2V; V
OL
= 0.4V
V
CC
< 2V; V
OL
= 0.2V
CC
V
CC
> 2V; V
OL
= 0.4V
1.7V < V
CC
< 2V;
V
OL
= 0.2V
CC
1.3V < V
CC
< 1.7V;
V
OL
= 0.2V
CC
(Note 5)
(Notes 6, 7)
(Notes 6, 7)
(Note 6)
100
SQW/INT Logic 0 Output
(Note 1)
mA
μA
μA
nA
nA
nA
I
OLSQW
Active Supply Current
Timekeeping Current
(Oscillator Enabled, INTCN = 1)
Timekeeping Current
(Oscillator Enabled, INTCN = 0)
Data Retention Current
(Oscillator Disabled)
I
CCA
I
OSC0
I
OSC1
I
DDR
150
800
1300
100
2 of 15
DS1371
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 1.7V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 8)
PARAMETER
SCL Clock Frequency (Note 9)
Bus Free Time Between STOP and
START Conditions
Hold Time (repeated) START Condition
(Note 10)
Low Period of SCL Clock
High Period of SCL Clock
Data Hold Time (Notes 11, 12)
Data Setup Time (Note 13)
Start Setup Time
Rise Time of Both SDA and SCL
Signals (Note 9)
Fall Time of Both SDA and SCL Signals
(Note 9)
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
(Note 7)
Pulse Width of Spikes that Must be
Suppressed by the Input Filter (Note 14)
Watchdog Strobe (WDS) Pulse Width
Oscillator Stop Flag (OSF) Delay
(Note 8)
SYMBOL
f
SCL
t
BUF
t
HD:STA
t
LOW
t
HIGH
t
HD:DAT
t
SU:DAT
t
SU:STA
t
R
CONDITIONS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
t
F
Standard mode
t
SU:STO
C
B
B
Fast mode
Standard mode
MIN
100
0
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0
0
100
250
0.6
4.7
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
20 +
0.1C
B
0.6
4.7
B
B
B
B
TYP
MAX
400
100
UNITS
kHz
μs
μs
μs
μs
0.9
0.9
μs
ns
μs
300
ns
1000
300
ns
300
μs
400
pF
ns
ns
ms
T
SP
t
WDS
t
OSF
Fast mode
100
100
30
Note 1:
All voltages are referenced to ground.
Note 2:
SCL and WDS only.
Note 3:
SDA and SQW/INT.
Note 4:
Limits at -40°C are guaranteed by design and not production tested.
Note 5:
I
CCA
—SCL clocking at max frequency = 400kHz. WDS inactive.
2
Note 6:
Specified with WDS input and I C bus inactive, SCL = SDA = V
CC
.
Note 7:
Measured with a 32.768kHz crystal attached to the X1 and X2 pins.
Note 8:
The parameter t
OSF
is the period of time the oscillator must be stopped in order for the OSF flag to be set over the voltage range of 1.3V
≤
V
CC
≤
V
CCMAX
.
Note 9:
A fast mode device can be used in a standard mode system, but the requirement t
SU:DAT
≥
to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of
the SCL signal, it must output the next data bit to the SDA line t
R MAX +
t
SU:DAT
= 1000 + 250 = 1250ns before the SCL line is released.
Note 10:
After this period, the first clock pulse is generated.
Note 11:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
IHMIN
of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
Note 12:
The maximum t
HD:DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
Note 13:
C
B
—total capacitance of one bus line in pF.
Note 14:
This parameter is not production tested.
B
3 of 15
DS1371
Typical Operating Characteristics
(V
CC
= 3.3V, T
A
= +25°C, unless otherwise noted.)
I
OSCO
vs. V
CC
SQUARE-WAVE OFF
DS1371 toc01
I
OSC1
vs. V
CC
SQUARE-WAVE ON
900
850
SUPPLY CURRENT (nA)
800
750
700
650
600
550
500
450
400
DS1371 toc02
600
550
SUPPLY CURRENT (nA)
500
450
400
350
300
1.5
2.0
2.5
3.0
3.5
V
CC
(V)
4.0
4.5
5.0
950
5.5
1.5
2.0
2.5
3.0
3.5
V
CC
(V)
4.0
4.5
5.0
5.5
I
OSC0
vs. TEMPERATURE
V
CC
= 3.3V
DS1371 toc03
I
CCA
vs. V
CC
SQUARE-WAVE ON
75
70
65
60
55
50
45
40
35
30
25
20
15
10
5
0
-40
-20
0
20
40
60
80
TEMPERATURE ( C)
DS1371 toc04
750
700
SUPPLY CURRENT (nA)
650
600
550
500
-40
-20
0
20
40
60
80
TEMPERATURE ( C)
I
OSC0
vs. WDS FREQUENCY
DS1371 toc05
SUPPLY CURRENT (µA)
OSCILLATOR FREQUENCY vs. V
CC
32767.76
DS1371 toc06
35
30
SUPPLY CURRENT (µA)
25
20
15
10
5
0
0
200
400
600
800
FREQUENCY (Hz)
1000
32767.71
32767.66
32767.61
3.767.56
1.3
1.8
2.3
2.8
3.3
3.8
4.3
4.8
5.3
V
CC
(V)
WDS FREQUENCY (kHz)
4 of 15
DS1371
Figure 1. Timing Diagram
X1
÷4
÷2
÷4096
32,768Hz
8192Hz
4096Hz
1Hz
M
U
X
SQW
M
U
X
N
SQW/INT
X2
V
CC
GND
WDS
Oscillator
CLR
DS1371
Power
Alarm/
Watchdog
Stat/Ctrl
SDA
SCL
I
2
C
Interface
WACE
4096Hz
1Hz
32-Bit
Counter
24-Bit
Counter
CLR
AIE
÷4096
1Hz
WD/ALM
M
U
X
INT
INTCN
Figure 2. Functional Diagram
5 of 15
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