or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
1-1
DS1004 Introduction_01.7
Lattice Semiconductor
Table 1-1. LatticeSC Family Selection Guide
1
Device
LUT4s (K)
sysMEM Blocks (18Kb)
Embedded Memory (Mbits)
Max. Distributed Memory (Mbits)
Number of 3.8Gbps SERDES (Max.)
DLLs
Analog PLLs
MACO Blocks
256-ball fpBGA (17 x 17mm)
900-ball fpBGA (31 x 31mm)
1020-ball fcBGA (33 x 33mm)
2
1152-ball fcBGA (35 x 35mm)
3
1704-ball fcBGA (42.5 x 42.5mm)
3
Introduction
LatticeSC/M Family Data Sheet
SC15
15
56
1.03
0.24
8
12
8
4
139/4
300/8
SC25
25
104
1.92
0.41
16
12
8
6
SC40
40
216
3.98
0.65
16
12
8
10
SC80
80
308
5.68
1.28
32
12
8
10
SC115
115
424
7.8
1.84
32
12
8
12
Package I/O/SERDES Combinations (1mm ball pitch)
378/8
476/16
562/16
604/16
660/16
904/32
660/16
942/32
1. The information in this preliminary data sheet is by definition not final and subject to change. Please consult the Lattice web site and your
local Lattice sales office to ensure you have the latest information regarding the specifications for these products as you make critical
design decisions.
2. Organic fcBGA converted to organic fcBGA revision 2 per
PCN #02A-10.
3. Ceramic fcBGA converted to organic fcBGA per
PCN #01A-10.
The LatticeSCM devices add MACO-enabled IP functionality to the base LatticeSC devices. Table 1-2 shows the
type and number of each pre-engineered IP core.
Table 1-2. LatticeSCM Family
Device
flexiMAC Blocks
• 1GbE Mode
• 10GbE Mode
• PCI Express Mode
SPI4.2 Blocks
Memory Controller Blocks
• DDR/DDR2 DRAM Mode
• QDR II/II+ SRAM Mode
• RLDRAM I
• RLDRAM II CIO/SIO
Low-Speed CDR Blocks
PCI Express LTSSM (PHY) Blocks
SCM15
1
1
SCM25
2
2
SCM40
2
2
SCM80
2
2
SCM115
4
2
1
2
2
2
2
0
1
0
0
2
2
2
2
2
2
Note: See each IP core user’s guide for more information about support for specific LatticeSCM devices.
Introduction
The LatticeSC family of FPGAs combines a high-performance FPGA fabric, high-speed SERDES, high-perfor-
mance I/Os and large embedded RAM in a single industry leading architecture. This FPGA family is fabricated in a
state of the art technology to provide one of the highest performing FPGAs in the industry.
This family of devices includes features to meet the needs of today’s communication network systems. These fea-
tures include SERDES with embedded advance PCS (Physical Coding sub-layer), up to 7.8 Mbits of sysMEM
embedded block RAM, dedicated logic to support system level standards such as RAPIDIO, SPI4.2, SFI-4, UTO-
PIA, XGMII and CSIX. The devices in this family feature clock multiply, divide and phase shift PLLs, numerous
1-2
Lattice Semiconductor
Introduction
LatticeSC/M Family Data Sheet
DLLs and dynamic glitch free clock MUXs which are required in today’s high end system designs. High-speed,
high-bandwidth I/O make this family ideal for high-throughput systems.
The ispLEVER
®
design tool from Lattice allows large complex designs to be efficiently implemented using the Lat-
ticeSC family of FPGA devices. Synthesis library support for LatticeSC is available for popular logic synthesis tools.
The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place
and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and back-
annotates it into the design for timing verification.
Lattice provides many pre-designed IP (Intellectual Property) ispLeverCORE™ modules for the LatticeSC family.
By using these IPs as standardized blocks, designers are free to concentrate on the unique aspects of their design,
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
京公网安备 11010802033920号
EEWORLD
