14-Bit, 20 MSPS/40 MSPS/65 MSPS
Dual A/D Converter
AD9248
FEATURES
Integrated dual 14-bit ADC
Single 3 V supply operation (2.7 V to 3.6 V)
SNR = 71.6 dB (to Nyquist, AD9248-65)
SFDR = 80.5 dBc (to Nyquist, AD9248-65)
Low power: 300 mW/channel at 65 MSPS
Differential input with 500 MHz, 3 dB bandwidth
Exceptional crosstalk immunity > 85 dB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary or twos complement data format
Clock duty cycle stabilizer
Output datamux option
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
OTR_A
VIN+_A
SHA
VIN–_A
ADC
14
OUTPUT
MUX/
BUFFERS
14
D13_A TO D0_A
OEB_A
REFT_A
REFB_A
VREF
SENSE
AGND
0.5V
MODE
CONTROL
REFT_B
CLOCK
DUTY CYCLE
STABILIZER
MUX_SELECT
CLK_A
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
APPLICATIONS
Ultrasound equipment
Direct conversion or IF sampling receivers
WB-CDMA, CDMA2000, WiMAX
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
REFB_B
VIN+_B
SHA
VIN–_B
ADC
OTR_B
14
OUTPUT 14
MUX/
BUFFERS
D13_B TO D0_B
OEB_B
04446-001
AD9248
DRVDD DRGND
Figure 1.
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20 MSPS/40 MSPS/65 MSPS
analog-to-digital converter (ADC). It features dual high
performance sample-and hold amplifiers (SHAs) and an
integrated voltage reference. The AD9248 uses a multistage
differential pipelined architecture with output error correction
logic to provide 14-bit accuracy and to guarantee no missing
codes over the full operating temperature range at up to
65 MSPS data rates. The wide bandwidth, differential SHA
allows for a variety of user-selectable input ranges and offsets,
including single-ended applications. It is suitable for various
applications, including multiplexed systems that switch full-
scale voltage levels in successive channels and for sampling
inputs at frequencies well beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available and can
compensate for wide variations in the clock duty cycle, allowing
the converter to maintain excellent performance. The digital
output data is presented in either straight binary or twos
complement format. Out-of-range signals indicate an overflow
condition, which can be used with the most significant bit to
determine low or high overflow.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Fabricated on an advanced CMOS process, the AD9248 is
available in a Pb-free, space saving, 64-lead LQFP or LFCSP and
is specified over the industrial temperature range (−40°C to
+85°C).
PRODUCT HIGHLIGHTS
1. Pin-compatible with the AD9238, 12-bit 20 MSPS/
40 MSPS/65 MSPS ADC.
2. Speed grade options of 20 MSPS, 40 MSPS, and 65 MSPS
allow flexibility between power, cost, and performance to suit
an application.
3. Low power consumption: AD9248-65: 65 MSPS = 600 mW,
AD9248-40: 40 MSPS = 330 mW, and AD9248-20: 20 MSPS =
180 mW.
4. Typical channel isolation of 85 dB @ f
IN
= 10 MHz.
5. The clock duty cycle stabilizer (AD9248-20/AD9248-40/
AD9248-65) maintains performance over a wide range of
clock duty cycles.
6. Multiplexed data output option enables single-port operation
from either Data Port A or Data Port B.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD9248
TABLE OF CONTENTS
Specifications..................................................................................... 3
DC Specifications ......................................................................... 3
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Absolute Maximum Ratings ............................................................ 8
Explanation of Test Levels ........................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Terminology .................................................................................... 11
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 16
Theory of Operation ...................................................................... 17
Analog Input ............................................................................... 17
Clock Input and Considerations .............................................. 18
Power Dissipation and Standby Mode ..................................... 19
Digital Outputs ........................................................................... 19
Timing.......................................................................................... 19
Data Format ................................................................................ 20
Voltage Reference ....................................................................... 20
AD9248 LQFP Evaluation Board ................................................. 22
Clock Circuitry ........................................................................... 22
Analog Inputs ............................................................................. 22
Reference Circuitry .................................................................... 22
Digital Control Logic ................................................................. 22
Outputs ........................................................................................ 22
LQFP Evaluation Board Bill of Materials (BOM) .................. 24
LQFP Evaluation Board Schematics ........................................ 25
LQFP PCB Layers ....................................................................... 29
Dual ADC LFCSP PCB .................................................................. 35
Power Connector........................................................................ 35
Analog Inputs ............................................................................. 35
Optional Operational Amplifier .............................................. 35
Clock ............................................................................................ 35
Voltage Reference ....................................................................... 35
Data Outputs ............................................................................... 35
LFCSP Evaluation Board Bill of Materials (BOM) ................ 36
LFCSP PCB Schematics ............................................................. 37
LFCSP PCB Layers ..................................................................... 40
Thermal Considerations............................................................ 45
Outline Dimensions ....................................................................... 46
Ordering Guide .......................................................................... 47
REVISION HISTORY
11/10—Rev. A to Rev. B
Changes to Absolute Maximum Ratings Section ......................... 8
Changes to Figure 3 .......................................................................... 9
Add Figure 4; Renumbered Sequentially ....................................... 9
Changes to Theory of Operation Section and Analog Input
Section .............................................................................................. 17
Deleted Note 1 from Dual ADC LFCSP PCB Section ............... 35
Updated Outline Dimensions ....................................................... 46
3/05—Rev. 0 to Rev. A
Added LFCSP ...................................................................... Universal
Changes to Features.......................................................................... 1
Changes to Applications .................................................................. 1
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Changes to Table 6 .......................................................................... 10
Changes to Terminology ............................................................... 11
Changes to Figure 22...................................................................... 15
Changes to Clock Input and Considerations Section ................ 18
Changes to Timing Section ........................................................... 19
Changes to Figure 33...................................................................... 19
Changes to Data Format Section .................................................. 20
Changes to Table 10 ....................................................................... 24
Changes to Figure 39...................................................................... 25
Changes to Table 13 ....................................................................... 36
Updated Outline Dimensions ....................................................... 46
Changes to Ordering Guide .......................................................... 47
1/05—Revision 0: Initial Version
Rev. B | Page 2 of 48
AD9248
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
IN
= −0.5 dBFS differential input, 1.0 V internal reference,
T
MIN
to T
MAX
, DCS enabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes Guaranteed
Offset Error
Gain Error
1
Differential Nonlinearity (DNL)
2
Integral Nonlinearity (INL)
2
Temp
Full
Full
25°C
Full
Full
25°C
Full
25°C
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
Test
Level
VI
VI
I
IV
V
IV
V
IV
V
V
VI
V
V
V
V
V
IV
IV
V
V
AD9248BST/BCP-20
Min Typ
Max
14
14
±0.2
±0.25
±0.65
±0.6
±2.7
±2.3
±2
±12
±5
0.8
±2.5
0.1
2.1
1.05
1
2
7
7
±35
±1.3
±2.2
±1.0
±4.5
AD9248BST/BCP-40
Min Typ
Max
14
14
±0.2
±0.3
±0.65
±0.6
±2.7
±2.3
±2
±12
±5
0.8
±2.5
0.1
2.1
1.05
1
2
7
7
±35
±1.3
±2.4
±1.0
±4.5
AD9248BST/BCP-65
Min Typ
Max
14
14
±0.2
±0.5
±0.7
±0.65
±2.8
±2.4
±3
±12
±5
0.8
±2.5
0.1
2.1
1.05
1
2
7
7
±35
±1.3
±2.5
±1.0
±4.5
Unit
Bits
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
ppm/°C
mV
mV
mV
mV
LSB rms
LSB rms
V p-p
V p-p
pF
kΩ
TEMPERATURE DRIFT
Offset Error
Gain Error
1
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
Output Voltage Error (0.5 V Mode)
Load Regulation @ 0.5 mA
INPUT REFERRED NOISE
Input Span = 1 V
Input Span = 2.0 V
ANALOG INPUT
Input Span = 1.0 V
Input Span = 2.0 V
Input Capacitance
3
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD
2
IDRVDD
2
PSRR
POWER CONSUMPTION
DC Input
4
Sine Wave Input
2
Standby Power
5
Full
Full
Full
Full
Full
Full
Full
Full
IV
IV
V
V
V
V
VI
V
2.7
2.25
3.0
3.0
60
5
±0.01
180
190
2.0
3.6
3.6
2.7
2.25
3.0
3.0
110
11
±0.01
330
360
2.0
3.6
3.6
2.7
2.25
3.0
3.0
200
16
±0.01
600
640
2.0
3.6
3.6
V
V
mA
mA
% FSR
mW
mW
mW
217
400
700
Rev. B | Page 3 of 48
AD9248
Parameter
MATCHING CHARACTERISTICS
Offset Error
(Nonshared Reference Mode)
Offset Error
(Shared Reference Mode)
Gain Error
(Nonshared Reference Mode)
Gain Error
(Shared Reference Mode)
1
2
Temp
25°C
25°C
25°C
25°C
Test
Level
I
I
I
I
AD9248BST/BCP-20
Min Typ
Max
±0.19
±0.19
±0.07
±0.01
±1.56
±1.56
±1.43
±0.06
AD9248BST/BCP-40
Min Typ
Max
±0.19
±0.19
±0.07
±0.01
±1.56
±1.56
±1.43
±0.06
AD9248BST/BCP-65
Min Typ
Max
±0.25
±0.25
±0.07
±0.01
±1.74
±1.74
±1.47
±0.10
Unit
% FSR
% FSR
% FSR
% FSR
Gain error and gain temperature coefficient are based on the ADC only (with a fixed 1.0 V external reference).
Measured at maximum clock rate with a low frequency sine wave input and approximately 5 pF loading on each output bit.
3
Input capacitance refers to the effective capacitance between one differential input pin and AVSS. Refer to Figure 29 for the equivalent analog input structure.
4
Measured with dc input at maximum clock rate.
5
Standby power is measured with the CLK_A and CLK_B pins inactive (that is, set to AVDD or AGND).
Rev. B | Page 4 of 48
AD9248
AC SPECIFICATIONS
AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; A
IN
= −0.5 dBFS differential input, 1.0 V external reference,
T
MIN
to T
MAX
, DCS Enabled, unless otherwise noted.
Table 2.
Parameter
SIGNAL-TO-NOISE RATIO (SNR)
f
INPUT
= 2.4 MHz
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 35 MHz
f
INPUT
= 100 MHz
SIGNAL-TO-NOISE AND DISTORTION
RATIO (SINAD)
f
INPUT
= 2.4 MHz
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 35 MHz
f
INPUT
= 100 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
f
INPUT
= 2.4 MHz
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 35 MHz
f
INPUT
= 100 MHz
WORST HARMONIC (SECOND or THIRD)
f
INPUT
= 2.4 MHz
f
INPUT
= 9.7 MHz
f
INPUT
= 19.6 MHz
f
INPUT
= 35 MHz
Temp
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Test
Level
V
IV
V
IV
V
IV
V
IV
V
AD9248BST/BCP-20
Min Typ
Max
73.4
73.7
72.9
73.1
AD9248BST/BCP-40
Min Typ
Max
73.1
73.4
AD9248BST/BCP-65
Min Typ
Max
72.8
73.1
Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
73.1
72.4
72.8
72.3
72.3
72.7
72.9
71.2
71.5
71.6
69.0
70
69.5
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
25°C
Full
25°C
Full
25°C
Full
25°C
Full
25°C
V
IV
V
IV
V
IV
V
IV
V
V
IV
V
IV
V
IV
V
IV
V
V
IV
V
I
V
I
V
I
72.2
70.9
73.0
73.2
72.0
72.2
72.0
72.8
73.0
71.7
72.5
72.7
71.0
72.1
72.3
70.0
70.9
71.0
68.5
11.8
11.8
69.5
11.8
11.8
11.7
11.7
69.0
11.8
11.8
dB
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
11.7
11.5
11.7
11.6
11.5
11.7
11.7
11.3
11.5
11.5
11.2
84.0
86.0
11.3
86.0
87.5
83.0
84.0
11.2
85.0
86.0
77.5
76.1
77.5
77.5
76.0
83.0
84.0
73.0
80.0
80.5
Rev. B | Page 5 of 48
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