NMI (non-maskable interrupt) and 128 peripheral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
USB device
USB2.0
On-Chip Memories
[Flash Memory]
These series are based on two independent on-chip Flash
memories.
MainFlash memory
Up
to 512 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
The read access to Flash memory can be achieved without
wait-cycle up to operation frequency of 72 MHz. Even at
the operation frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
Full-Speed supported
Max 6 Endpoint supported
• Endpoint 0 is control transfer
• Endpoint 1, 2 can be selected Bulk-transfer,
Interrupt-transfer or Isochronous-transfer
• Endpoint 3 to 5 can select Bulk-transfer or
Interrupt-transfer
• Endpoint 1 to 5 comprise Double Buffer
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64 bytes
• Endpoint 1: 256 bytes
USB host
USB2.0
WorkFlash memory
Kbytes
Read cycle:
• 6wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
• 4wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
Cypress Semiconductor Corporation
Document Number: 002-04922 Rev.*B
32
Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet automatically
Max 256-byte packet-length supported
Wake-up function supported
CAN Interface (1 Channel)
Compatible with CAN Specification 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised December 15, 2017
MB9B560L Series
Multi-Function Serial Interface (Max 6 Channels)
64 bytes with FIFO (the FIFO step numbers are variable
depending on the settings of the communication mode or bit
length.)
DSTC (Descriptor System data Transfer Controller)
(128 Channels)
The DSTC can transfer data at high-speed without going via
the CPU. The DSTC adopts the Descriptor system and,
following the specified contents of the Descriptor which has
already been constructed on the memory, can access directly
the memory /peripheral device and performs the data transfer
operation.
It supports the software activation, the hardware activation and
the chain activation functions.
Operation mode is selectable from the followings for each
channel.
UART
CSIO
LIN
2
I C
UART
double buffer
Selection with or without parity supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
Full-duplex
A/D Converter (Max 15 Channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 0.5 μs @ 5 V
Priority conversion available (priority at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SCAN
conversion: 16steps, for Priority conversion: 4steps)
CSIO
Full-duplex
double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 only)
Supports high-speed SPI (ch.0 and ch.6 only)
Data length 5 to 16-bit
DA Converter (Max 2 Channels)
R-2R type
12-bit resolution
Base Timer (Max 8 Channels)
Operation mode is selectable from the followings for each
channel.
LIN
protocol Rev.2.1 supported
Full-duplex double buffer
Master/Slave mode supported
LIN break field generation (can change to 13 to 16-bit
length)
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect functions available (parity errors,
framing errors, and overrun errors)
I
2
C
Standard mode (Max 100 kbps) / Fast-mode (Max 400
kbps) supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A
and ch.4=ch.B) supported
LIN
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series can use its pins as general purpose I/O ports when
they are not used for external bus or peripherals. Moreover, the
port relocate function is built in. It can set which I/O port the
peripheral function can be allocated.
DMA Controller (8 Channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can process simultaneously.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 48 high-speed general-purpose I/O ports @ 64 pin
Package
8 independently configured and operated channels
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Some pin is 5 V tolerant I/O.
See 4. Pin Description and 5. I/O Circuit Type for the
corresponding pins.
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
Document Number: 002-04922 Rev.*B
Page 2 of 128
MB9B560L Series
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down
counters.
Operation mode is selectable from the followings for each
channel.
Multi-Function Timer (Max 2 Units)
The Multi-function timer is composed of the following blocks.
Minimum resolution: 6.25 ns
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 6 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up from the low-power
consumption mode. It is possible to select the main clock, sub
clock, built-in high-speed CR clock or built-in low-speed CR
clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture function
A/D convertor activate function
DTIF (Motor emergency stop) interrupt function
Real-Time Clock (RTC)
The Real-time clock can count
Year/Month/Day/Hour/Minute/Second/A day of the week from
00 to 99.
External Interrupt Controller Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (2 Channels)
A watchdog timer can generate interrupts or a reset when a
time-out value is reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked by low-speed internal
CR oscillator. Therefore, "Hardware" watchdog is active in any
power saving mode except STOP.
Interrupt function with specifying date and time
(Year/Month/Day/Hour/Minute) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or
storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
Timer interrupt function after set time or each set time.
Capable of rewriting the time with continuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC) (1
Channel)
The Quadrature Position/Revolution Counter (QPRC) is used
to measure the position of the position encoder. Moreover, it is
possible to use up/down counter.
CCITT CRC16 Generator Polynomial: 0x1021
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
The detection edge of the three external event input pins AIN,
BIN, and ZIN is configurable.
16-bit position counter
16-bit revolution counter
Two 16-bit compare registers
Document Number: 002-04922 Rev.*B
Page 3 of 128
MB9B560L Series
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamically selectable.
VBAT
The consumption power during the RTC operation can be
reduced by supplying the power supply independent from the
RTC (calendar circuit)/32 kHz oscillation circuit. The following
circuits can also be used.
Main clock:
Sub Clock:
4 MHz to 48 MHz
32.768 kHz
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Unique ID
Unique value of the device (41-bit) is set.
High-speed internal CR Clock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers reset
Low voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks generated by internal CR oscillators are used to
supervise abnormality of the external clocks.
Power Supply
Three Power Supplies (when 64 pin Package)
Two Power Supplies (when 48 pin Package)
Wide range voltage:
VCC
= 2.7 V to 5.5 V
Power supply for USB I/O:
USBVCC = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
External OSC clock failure (clock stop) is detected, reset is
asserted.
External OSC frequency anomaly is detected, interrupt or
reset is asserted.
Power supply for VBAT (only 64 pin Package):
VBAT
= 2.7 V to 5.5 V
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the VCC
pins. When the voltage falls below the voltage has been set,
Low-Voltage Detector generates an interrupt or reset.
LVD1: error reporting via interrupt
LVD2: auto-reset operation
Low-Power Consumption Mode
Six low-power consumption modes are supported.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectable from with/without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
Document Number: 002-04922 Rev.*B
Page 4 of 128
MB9B560L Series
Contents
Features ................................................................................................................................................................................... 1
List of Pin Numbers ..................................................................................................................................................... 13
4.2
List of Pin Functions .................................................................................................................................................... 19
5. I/O Circuit Type ............................................................................................................................................................... 28
Precautions for Product Design ................................................................................................................................... 35
6.2
Precautions for Package Mounting .............................................................................................................................. 36
6.3
Precautions for Use Environment ................................................................................................................................ 37
11. Pin Status in Each CPU State ........................................................................................................................................ 45
12.3 DC Characteristics ...................................................................................................................................................... 57
12.3.1 Current Rating .............................................................................................................................................................. 57
12.4 AC Characteristics ....................................................................................................................................................... 66
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 66
12.4.2 Sub Clock Input Characteristics ................................................................................................................................... 67
C Timing ............................................................................................................................................................... 100
12.7 USB Characteristics .................................................................................................................................................. 107
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