Register Map: Section
6.2
ZL30250, ZL30251
4-Input, 3-Output Any-to-Any Clock
Multiplier and Frequency Synthesizer ICs
Data Sheet
January 2018
Features
•
Four Input Clocks
•
One crystal/CMOS input
•
Two differential/CMOS inputs
•
One single-ended/CMOS input
•
Any input frequency from 9.72MHz to 1250MHz
(9.72MHz to 300MHz for CMOS)
•
Clock selection by pin or register control
•
Low-Jitter Fractional-N APLL and 3 Outputs
•
Any output frequency from <1Hz to 1035MHz
•
High-resolution fractional frequency conversion
with 0ppm error
•
Easy-to-configure, encapsulated design
requires no external VCXO or loop filter
components
•
Each output has independent dividers
•
Output jitter as low as 0.16ps RMS (12kHz-
20MHz integration band)
•
Outputs are CML or 2xCMOS, can interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
•
In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
•
Per-output supply pin with CMOS output
voltages from 1.5V to 3.3V
Ordering Information
ZL30250LDG1
ZL30250LDF1
ZL30251LDG1
ZL30251LDF1
32 Pin QFN
32 Pin QFN
32 Pin QFN
32 Pin QFN
Matte Tin
Package size: 5 x 5 mm
-40
C to +85
C
Trays
Tape and Reel
Trays
Tape and Reel
•
Precise output alignment circuitry and per-
output phase adjustment
•
Per-output enable/disable and glitchless
start/stop (stop high or low)
•
General Features
•
Automatic self-configuration at power-up from
external (ZL30250) or internal (ZL30251)
EEPROM; up to four configs, pin-selectable
•
SPI or I
2
C processor Interface
•
Numerically controlled oscillator mode
•
Spread-spectrum modulation mode
•
Tiny 5x5mm QFN package
•
Easy-to-use evaluation software
Applications
•
Frequency conversion and frequency synthesis in
a wide variety of equipment types
IC1P, IC1N
IC2P, IC2N
IC3P/GPIO3
XA
XB
xtal
driver
HSDIV1
HSDIV2
HSDIV3
×2
APLL
NCO
SS
~3.7 to 4.2GHz,
Fractional-N
HSDIV1
DIV1
DIV2
Figure 6
HSDIV2
DIV3
OC1P, OC1N
VDDO1
OC2P, OC2N
VDDO2
OC3P, OC3N
VDDO3
(SPI or I2C Serial)
and HW Control and Status Pins
Microprocessor Port
AC0/GPIO0
AC1/GPIO1
TEST/GPIO2
IC3P/GPIO3
RSTN
IF0/CSN
SCL/SCLK
Figure 1 - Functional Block Diagram
1
Microsemi Confidential
Copyright 2018. Microsemi Corporation. All Rights Reserved.
SDA/MOSI
IF1/MISO
ZL30250, ZL30251
Data Sheet
Table of Contents
1.
2.
2.1
2.2
2.3
2.4
2.5
3.
4.
5.
5.1
5.2
5.3
APPLICATION EXAMPLES .......................................................................................................... 5
DETAILED FEATURES ................................................................................................................. 5
I
NPUT
C
LOCK
F
EATURES
.............................................................................................................. 5
APLL F
EATURES
.......................................................................................................................... 5
O
UTPUT
C
LOCK
F
EATURES
........................................................................................................... 5
G
ENERAL
F
EATURES
.................................................................................................................... 5
E
VALUATION
S
OFTWARE
............................................................................................................... 6
PIN DIAGRAM ............................................................................................................................... 6
PIN DESCRIPTIONS ..................................................................................................................... 7
FUNCTIONAL DESCRIPTION ...................................................................................................... 9
D
EVICE
I
DENTIFICATION
................................................................................................................ 9
P
IN
-C
ONTROLLED
A
UTOMATIC
C
ONFIGURATION AT
R
ESET
............................................................. 9
ZL30250—External EEPROM or No EEPROM ................................................................................... 10
ZL30251—Internal EEPROM ............................................................................................................... 10
External Oscillator ................................................................................................................................ 11
External Crystal and On-Chip Driver Circuit ........................................................................................ 11
Clock Doubler ....................................................................................................................................... 12
Ring Oscillator (for System Start-Up) ................................................................................................... 12
5.2.1
5.2.2
5.3.1
5.3.2
5.3.3
5.3.4
L
OCAL
O
SCILLATOR OR
C
RYSTAL
................................................................................................ 10
5.4
5.5
5.6
I
NPUT
S
IGNAL
F
ORMAT
C
ONFIGURATION
...................................................................................... 12
N
UMERICALLY
C
ONTROLLED
O
SCILLATOR
/ S
PREAD
S
PECTRUM
B
LOCK
(NCO/SS)........................ 13
Numerically Controlled Oscillator (NCO) Mode ................................................................................... 13
Spread-Spectrum Modulation Mode .................................................................................................... 13
APLL Input Selection and Frequency .................................................................................................. 14
APLL Output Frequency....................................................................................................................... 14
APLL Phase Adjustment ...................................................................................................................... 15
5.5.1
5.5.2
5.6.1
5.6.2
5.6.3
APLL C
ONFIGURATION
............................................................................................................... 14
5.7
O
UTPUT
C
LOCK
C
ONFIGURATION
................................................................................................ 15
5.7.1
Output Enable, Signal Format, Voltage and Interfacing ...................................................................... 16
5.7.2
Output Frequency Configuration .......................................................................................................... 16
5.7.3
Output Duty Cycle Adjustment ............................................................................................................. 17
5.7.4
Output Phase Adjustment and Phase Alignment ................................................................................. 17
5.7.4.1
Phase Adjustment ......................................................................................................................... 17
5.7.4.2
Phase Alignment, Output-to-Output.............................................................................................. 18
5.7.4.3
Phase Alignment, Input-to-Output ................................................................................................ 19
5.7.5
Output Clock Start and Stop ................................................................................................................ 19
5.7.6
A-to-B Phase Offset Measurement ...................................................................................................... 20
5.8
M
ICROPROCESSOR
I
NTERFACE
................................................................................................... 23
SPI Slave ............................................................................................................................................. 23
SPI Master (ZL30250 Only) ................................................................................................................. 25
I
2
C Slave .............................................................................................................................................. 26
5.8.1
5.8.2
5.8.3
5.9 I
NTERRUPT
L
OGIC
...................................................................................................................... 28
5.10
R
ESET
L
OGIC
.......................................................................................................................... 29
5.11
P
OWER
-S
UPPLY
C
ONSIDERATIONS
.......................................................................................... 29
5.12
A
UTO
-C
ONFIGURATION FROM
EEPROM .................................................................................. 29
5.12.1
5.12.2
5.12.3
Generating Device Configurations ....................................................................................................... 29
Direct EEPROM Write Mode (ZL30251 Only) ..................................................................................... 30
Holding Other Devices in Reset During Auto-Configuration ................................................................ 30
2
Microsemi Confidential
ZL30250, ZL30251
5.13
6.
6.1
Data Sheet
P
OWER
S
UPPLY
D
ECOUPLING AND
L
AYOUT
R
ECOMMENDATIONS
............................................... 30
R
EGISTER
T
YPES
....................................................................................................................... 30
Status Bits ............................................................................................................................................ 30
Configuration Fields ............................................................................................................................. 30
Multiregister Fields ............................................................................................................................... 30
Bank-Switched Registers (ZL30251 Only) ........................................................................................... 31
REGISTER DESCRIPTIONS ....................................................................................................... 30
6.1.1
6.1.2
6.1.3
6.1.4
6.2
6.3
R
EGISTER
M
AP
.......................................................................................................................... 31
R
EGISTER
D
EFINITIONS
.............................................................................................................. 33
Global Configuration Registers ............................................................................................................ 33
Status Registers ................................................................................................................................... 41
APLL Configuration Registers .............................................................................................................. 49
Output Clock Configuration Registers .................................................................................................. 55
Input Clock Configuration Registers .................................................................................................... 61
NCO/Spread-Spectrum Configuration Registers ................................................................................. 61
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
7.
8.
ELECTRICAL CHARACTERISTICS ........................................................................................... 63
PACKAGE AND THERMAL INFORMATION .............................................................................. 74
8.1 P
ACKAGE
T
OP
M
ARK
F
ORMAT
..................................................................................................... 74
8.2 T
HERMAL
S
PECIFICATIONS
.......................................................................................................... 75
MECHANICAL DRAWING .......................................................................................................... 76
ACRONYMS AND ABBREVIATIONS ......................................................................................... 77
DATA SHEET REVISION HISTORY ........................................................................................... 77
9.
10.
11.
3
Microsemi Confidential
ZL30250, ZL30251
Data Sheet
List of Figures
Figure 1 - Functional Block Diagram ........................................................................................................................... 1
Figure 2 - Ethernet Frequency Synthesis Application ................................................................................................. 5
Figure 3 - PCI Express Frequency Multiplication Application ...................................................................................... 5
Figure 4 - Pin Diagram ................................................................................................................................................. 6
Figure 5 - Crystal Equivalent Circuit / Recommended Crystal Circuit ....................................................................... 11
Figure 6 - APLL Block Diagram ................................................................................................................................. 14
Figure 7 - SPI Read Transaction Functional Timing.................................................................................................. 24
Figure 8 - SPI Write Enable Transaction Functional Timing (ZL30251 Only) ........................................................... 24
Figure 9 - SPI Write Transaction Functional Timing .................................................................................................. 25
Figure 10 – I
2
C Read Transaction Functional Timing ................................................................................................ 27
Figure 11 – I
2
C Register Write Transaction Functional Timing ................................................................................. 27
Figure 12 – I
2
C EEPROM Write Transaction Functional Timing (ZL30251 Only) ..................................................... 27
Figure 13 – I
2
C EEPROM Read Status Transaction Functional Timing (ZL30251 Only) ......................................... 27
Figure 14 – Interrupt Structure ................................................................................................................................... 28
Figure 15 - Electrical Characteristics: Clock Inputs ................................................................................................... 65
Figure 16 - Example External Components for Differential Input Signals ................................................................. 66
Figure 17 - Electrical Characteristics: CML Clock Outputs........................................................................................ 67
Figure 18 – Example External Components for CML Output Signals ....................................................................... 67
Figure 19 – Example External Components for HCSL Output Signals ..................................................................... 68
Figure 20 - SPI Slave Interface Timing ...................................................................................................................... 70
Figure 21 - SPI Master Interface Timing .................................................................................................................... 72
Figure 22 - I
2
C Slave Interface Timing ....................................................................................................................... 73
Figure 23 - Non-customized Device Top Mark .......................................................................................................... 74
Figure 24 - Custom Factory Programmed Device Top Mark ..................................................................................... 74
List of Tables
Table 1 - Pin Descriptions ............................................................................................................................................ 7
Table 2 - Crystal Selection Parameters ..................................................................................................................... 12
Table 3 – SPI Commands .......................................................................................................................................... 23
Table 4 - Register Map .............................................................................................................................................. 31
Table 5 - Recommended DC Operating Conditions .................................................................................................. 63
Table 6 - Electrical Characteristics: Supply Currents ................................................................................................ 63
Table 7 - Electrical Characteristics: Non-clock CMOS Pins ...................................................................................... 64
Table 8 - Electrical Characteristics: XA Clock Input .................................................................................................. 64
Table 9 - Electrical Characteristics: Clock Inputs, ICxP/N ......................................................................................... 65
Table 10 - Electrical Characteristics: CML Clock Outputs ......................................................................................... 66
Table 11 - Electrical Characteristics: CMOS and HSTL (Class I) Clock Outputs ...................................................... 68
Table 12 - Electrical Characteristics: APLL Frequencies .......................................................................................... 68
Table 13 - Electrical Characteristics: Jitter Specifications ......................................................................................... 69
Table 14 - Electrical Characteristics: Typical Output Jitter Performance .................................................................. 69
Table 15 - Electrical Characteristics: Typical Input-to-Output Clock Delay ............................................................... 69
Table 16 - Electrical Characteristics: Typical Output-to-Output Clock Delay ............................................................ 69
Table 17 - Electrical Characteristics: SPI Slave Interface Timing, Device Registers ................................................ 70
Table 18 - Electrical Characteristics: SPI Slave Interface Timing, Internal EEPROM (ZL30251 Only) .................... 71
Table 19 - Electrical Characteristics: SPI Master Interface Timing (ZL30250 Only) ................................................. 72
Table 20 - Electrical Characteristics: I
2
C Slave Interface Timing .............................................................................. 73
Table 21 – Package Top Mark Legend ..................................................................................................................... 74
Table 22 - 5x5mm QFN Package Thermal Properties .............................................................................................. 75
4
Microsemi Confidential
ZL30250, ZL30251
1. Application Examples
2x 156.25MHz differential
50MHz
Data Sheet
ZL3025x
125MHz CMOS
25MHz CMOS
Frequency synthesis from crystal resonator
Figure 2 - Ethernet Frequency Synthesis Application
25MHz
ZL3025x
3x 100MHz differential
Frequency multiplication from input clock signal
Figure 3 - PCI Express Frequency Multiplication Application
2. Detailed Features
2.1
Input Clock Features
•
•
Four input clocks: one crystal/CMOS, two differential/CMOS, one single-ended/CMOS
Input clocks can be any frequency from 9.72MHz up to 1250MHz (differential) or 300MHz (CMOS)
Very high-resolution fractional (i.e. non-integer) multiplication
Any-to-any frequency conversion with 0ppm error
Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
Bypass mode supports system testing
Three low-jitter output clocks
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)
Output jitter as low as 0.16ps RMS (12kHz to 20MHz integration band)
In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
(example: OC3P 125MHz, OC3N 25MHz)
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Can produce PCIe clocks (PCIe gen. 1, 2 and 3)
Sophisticated output-to-output phase alignment
Per-output phase adjustment with high resolution and unlimited range
Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
SPI or I
2
C serial microprocessor interface
Automatic self-configuration at power-up from external (ZL30250) or internal (ZL30251) EEPROM
memory; pin control to specify one of four stored configurations
2.2
APLL Features
•
•
•
•
•
2.3
Output Clock Features
•
•
•
•
•
•
•
•
•
•
•
•
•
2.4
General Features
•
•
5
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