DAC1208D750
Dual 12-bit DAC; up to 750 Msps; 2, 4 or 8 interpolating
with JESD204A interface
Rev. 04 — 2 July 2012
Product data sheet
1. General description
The DAC1208D750 is a high-speed 12-bit dual channel Digital-to-Analog Converter
(DAC) with selectable 2, 4 or 8 interpolating filters optimized for multi-carrier WCDMA
transmitters.
Because of its digital on-chip modulation, the DAC1208D750 allows the complex pattern
provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to
IF. The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit
Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1208D750 also includes a 2, 4 or 8 clock multiplier which provides the
appropriate internal clocks and an internal regulation to adjust the output full-scale
current.
The input data format is serial according to JESD204A specification. This new interface
has numerous advantages over the traditional parallel one: easy PCB layout, lower
radiated noise, lower pin count, self-synchronous link, skew compensation. The maximum
number of lanes of the DAC1208D750 is 4 and its maximum serial data rate is
3.125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output
clock period between several DAC devices. MDS incorporates modes: Master/slave and
All slave mode.
2. Features and benefits
Dual 12-bit resolution
750 Msps maximum update rate
Selectable 2, 4 or 8 interpolation
filters
Input data rate up to 312.5 Msps
Very low noise cap free integrated PLL
32-bit programmable NCO frequency
Four JESD204A serial input lanes
1.8 V and 3.3 V power supplies
LVDS compatible clock inputs
IMD3: 80 dBc; f
s
= 737.28 Msps;
f
o
= 140 MHz
ACPR: 71 dBc; 2 carriers WCDMA;
f
s
= 737.28 Msps; f
o
= 153.6 MHz
Typical 1.27 W power dissipation at 4
interpolation, PLL off and 740 Msps
Power-down mode and Sleep modes
Differential scalable output current from
1.6 mA to 22 mA
On-chip 1.29 V reference
External analog offset control
(10-bit auxiliary DACs)
Internal digital offset control
Inverse (sin x) / x function
®
Integrated Device Technology
DAC1208D750
2, 4 or 8 interpolating DAC with JESD204A
Two’s complement or binary offset data
Fully compatible SPI port
format
LMF = 421 or LMF = 211 support
Industrial temperature range from
40 C
to +85
C
Differential CML receiver with
Integrated PLL can be bypassed
embedded termination
Synchronization of multiple DAC outputs
Embedded complex modulator
3. Applications
Wireless infrastructure: LTE, WiMAX, GSM, CDMA, WCDMA, TD-SCDMA
Communication: LMDS/MMDS, point-to-point
Direct Digital Synthesis (DDS)
Broadband wireless systems
Digital radio links
Instrumentation
Automated Test Equipment (ATE)
4. Ordering information
Table 1.
Ordering information
Package
Name
DAC1208D750HN
HVQFN64
Description
Version
plastic thermal enhanced very thin quad flat package; no leads; SOT804-3
64 terminals; body 9
9
0.85 mm
Type number
DAC1208D750 4
© IDT All rights reserved.
Product data sheet
Rev. 04 — 2 July 2012
2 of 96
5. Block diagram
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INTER LANE ALIGNMENT
VIN_P1
L1
VIN_N1
LANE
PROC
FRAME ASSEMBLY
Product data sheet
Rev. 04 — 2 July 2012
3 of 96
DAC1208D750 4
© IDT All rights reserved.
Integrated Device Technology
SDO
SDIO
SCS_N
SCLK
SPI CONTROL REGISTERS
NCO
32-bit frequency setting
16-bit phase adjustment
cos
sin
10-BIT
OFFSET
CONTROL
AUX.
DAC
AUXAP
AUXAN
SYNC_OUTP
SYNC_OUTN
DIGITAL LAYER
PROCESSING
JESD204A
LANE
PROC
10-BIT
GAIN
CONTROL
FIR 1
FIR 2
FIR 3
x
sin x
Σ
I DAC
IOUTAN
IOUTAP
+
VIN_P0
L0
VIN_N0
2
×
2
×
2
×
DAC1208D750HN
VIN_P2
L2
VIN_N2
SINGLE
SIDE
BAND
MODULATOR
FIR 3
OFFSET
CONTROL
REF.
BANDGAP
AND
BIASING
VIRES
GAPOUT
LANE
PROC
FIR 1
FIR 2
2, 4 or 8 interpolating DAC with JESD204A
VIN_P3
L3
VIN_N3
LANE
PROC
2
×
2
×
2
×
x
sin x
+
Σ
Q DAC
IOUTBP
IOUTBN
10-BIT
GAIN
CONTROL
CLOCK GENERATOR UNIT
MULTI-DAC
SYNCHRONIZATION
10-BIT
OFFSET
CONTROL
AUX.
DAC
AUXBP
AUXBN
DAC1208D750
CLKINP
CLKINN
RESET_N
MDS_P
MDS_N
001aam758
Fig 1.
Block diagram
Integrated Device Technology
DAC1208D750
2, 4 or 8 interpolating DAC with JESD204A
6. Pinning information
6.1 Pinning
50 SYNC_OUTN
51 SYNC_OUTP
59 V
DDD(1V8)
54 V
DDD(1V8)
terminal 1
index area
SDO
SDIO
SCLK
V
DDD(1V8)
SCS_N
RESET_N
n.c.
VIRES
GAPOUT
1
2
3
4
5
6
7
8
9
49 V
DDD(1V8)
48 n.c.
47 V
DDD(1V8)
46 MDS_N
45 MDS_P
44 V
DDA(1V8)
43 AGND
42 CLKINN
41 CLKINP
40 AGND
39 V
DDA(1V8)
38 V
DDA(1V8)
37 AGND
36 AUXAN
35 AUXAP
34 V
DDA(3V3)
33 AGND
V
DDA(1V8)
32
001aam759
61 VIN_N3
57 VIN_N2
56 VIN_N1
DAC1208D750HN
V
DDA(1V8)
10
V
DDA(1V8)
11
AGND 12
AUXBN 13
AUXBP 14
V
DDA(3V3)
15
AGND 16
V
DDA(1V8)
17
AGND 18
V
DDA(1V8)
19
V
DDA(1V8)
20
AGND 21
IOUTBN 22
IOUTBP 23
AGND 24
AGND 25
IOUTAP 26
IOUTAN 27
AGND 28
V
DDA(1V8)
29
V
DDA(1V8)
30
AGND 31
Transparent top view
Fig 2.
Pin configuration
6.2 Pin description
Table 2.
Symbol
SDO
SDIO
SCLK
V
DDD(1V8)
SCS_N
RESET_N
n.c.
VIRES
GAPOUT
V
DDA(1V8)
V
DDA(1V8)
DAC1208D750 4
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
Type
[1]
O
I/O
I
P
I
I
-
I/O
I/O
P
P
Description
SPI data output
SPI data input/output
SPI clock
digital supply voltage 1.8 V
SPI chip select (active LOW)
general reset (active LOW)
not connected
DAC biasing resistor
band gap input/output voltage
analog supply voltage 1.8 V
analog supply voltage 1.8 V
© IDT All rights reserved.
Product data sheet
Rev. 04 — 2 July 2012
52 VIN_N0
60 VIN_P3
58 VIN_P2
55 VIN_P1
53 VIN_P0
64 JTAG
63 n.c.
62 n.c.
4 of 96
Integrated Device Technology
DAC1208D750
2, 4 or 8 interpolating DAC with JESD204A
Table 2.
Symbol
AGND
AUXBN
AUXBP
V
DDA(3V3)
AGND
V
DDA(1V8)
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
IOUTBN
IOUTBP
AGND
AGND
IOUTAP
IOUTAN
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
V
DDA(1V8)
AGND
V
DDA(3V3)
AUXAP
AUXAN
AGND
V
DDA(1V8)
V
DDA(1V8)
AGND
CLKINP
CLKINN
AGND
V
DDA(1V8)
MDS_P
MDS_N
V
DDD(1V8)
n.c.
V
DDD(1V8)
Pin description
…continued
Pin
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
Type
[1]
G
O
O
P
G
P
G
P
P
G
O
O
G
G
O
O
G
P
P
G
P
G
P
O
O
G
P
P
G
I
I
G
P
I/O
I/O
P
-
P
O
O
Description
analog ground
complementary auxiliary DAC B output
auxiliary DAC B output
analog supply voltage 3.3 V
analog ground
analog supply voltage 1.8 V
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
complementary DAC B output current
DAC B output current
analog ground
analog ground
DAC A output current
complementary DAC A output current
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
analog supply voltage 1.8 V
analog ground
analog supply voltage 3.3 V
auxiliary DAC A output current
complementary auxiliary DAC A output current
analog ground
analog supply voltage 1.8 V
analog supply voltage 1.8 V
analog ground
clock input
complementary clock input
analog ground
analog supply voltage 1.8 V
multi-device synchronization
complementary multi-device synchronization
digital supply voltage 1.8 V
not connected
digital supply voltage 1.8 V
synchronization request to transmitter, complementary
output
synchronization request to transmitter
© IDT All rights reserved.
SYNC_OUTN
SYNC_OUTP
DAC1208D750 4
Product data sheet
Rev. 04 — 2 July 2012
5 of 96
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