The SY89825U is a High Performance Bus Clock Driver
with 22 differential LVPECL output pairs. This part is
designed for use in low voltage (2.5V, 3.3V) applications
which require a large number of outputs to drive precisely
aligned, ultra low skew signals to their destination. The
input is multiplexed from either LVDS or LVPECL by the
CLK_SEL pin. The LVDS input includes a 100Ω internal
termination, thus eliminating the need for external
termination. The Output Enable (OE) is synchronous so
that the outputs will only be enabled/disabled when they
are already in the LOW state. This eliminates any chance
of generating a runt clock pulse when the device is enabled/
disabled as can happen with an asynchronous control.
The SY89825U features low pin-to-pin skew (35ps max.)
—performance previously unachievable in a standard
product having such a high number of outputs. The
SY89825U is available in a single space saving package
which provides a lower overall cost solution. In addition, a
single chip solution improves timing budgets by eliminating
the multiple device solution with their corresponding large
part-to-part skew.
• > 2GHz f
MAX
(toggle)
• < 35ps max. ch-ch skew
s
Low voltage operation: 2.5V, 3.3V
s
Temperature range: –40
°
C to +85
°
C
s
Output enable pin
s
Available in a 64-Pin EPAD-TQFP
APPLICATIONS
s
High-performance PCs
s
Workstations
s
Parallel processor-based systems
s
Other high-performance computing
s
Communications
Precision Edge is a registered trademark of Micrel, Inc.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
Rev.: D
Amendment: /0
1
Issue Date: January 2007
Micrel, Inc.
Precision Edge
®
SY89825U
PACKAGE/ORDERING INFORMATION
Ordering Information
(1)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VCCO
Q7
/Q7
Q8
/Q8
Q9
/Q9
Q10
/Q10
Q11
/Q11
Q12
/Q12
Q13
/Q13
VCCO
VCCO
/Q6
Q6
/Q5
Q5
/Q4
Q4
/Q3
Q3
/Q2
Q2
/Q1
Q1
/Q0
Q0
VCCO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VCCO
NC
NC
VCCI
LVDS_CLK
/LVDS_CLK
CLK_SEL
LVPECL_CLK
/LVPECL_CLK
GND
OE
NC
NC
/Q21
Q21
VCCO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Part Number
SY89825UHI
SY89825UHITR
(2)
SY89825UHY
(3)
SY89825UHYTR
(2,3)
Package Operating
Type
Range
H64-1
H64-1
H64-1
H64-1
Industrial
Industrial
Industrial
Industrial
Package
Marking
SY89825UHI
SY89825UHI
Lead
Finish
Sn-Pb
SN-PB
64-Pin
EPAD-TQFP
(Top View)
SY89825UHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
SY89825UHY with
Pb-Free
Pb-Free bar-line indicator Matte-Sn
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64-Pin EPAD-TQFP (H64-1)
VCCO
/Q20
Q20
/Q19
Q19
/Q18
Q18
/Q17
Q17
/Q16
Q16
/Q15
Q15
/Q14
Q14
VCCO
Notes:
1. Contact factory for die availability. Dice are guaranteed at T
A
= 25°C, DC electricals only.
2. Tape and Reel.
3. Pb-Free package recommended for new designs.
PIN NAMES
Pin
LVDS_CLK,
/LVDS_CLK
LVPECL_CLK,
/LVPECL_CLK
CLK_SEL
OE
Q
0
– Q
21
, /Q
0
– /Q
21
GND
V
CCI
Function
Differential LVDS Inputs
(Internal 100Ω termination included)
Differential LVPECL Inputs.
Input CLK Select (LVTTL)
Output Enable (LVTTL)
Differential LVPECL Outputs.
Terminate with 50Ω to V
CC
-2V
Ground
Power Supply. Connect to
V
CC
on PCB. V
CCI
and V
CCO
are not
internally connected
Power Supply for Output Buffer.
Connect to V
CCI
on PCB. V
CCI
and
V
CCO
are not internally connected
LOGIC SYMBOL
CLK_SEL
LVDS_CLK
/LVDS_CLK
0
22
22
Q0 - Q21
/Q0 - /Q21
LVPECL_CLK
1
/LVPECL_CLK
LEN
Q
OE
D
V
CCO
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge
®
SY89825U
TRUTH TABLE
OE
(1)
0
0
1
1
CLK_SEL
0
1
0
1
Q
0
– Q
21
LOW
LOW
LVDS_CLK
LVPECL_CLK
/Q
0
– /Q
21
HIGH
HIGH
/LVDS_CLK
/LVPECL_CLK
SIGNAL GROUPS
Signal
LVDS_CLK, /LVDS_CLK
Q
0
– Q
21
, /Q
0
– /Q
21
LVPECL_CLK, /LVPECL_CLK
CLK_SEL, OE
I/O
Input
Output
Input
Input
LVDS
LVPECL
LVPECL
LVCMOS/LVTTL
Level
NOTE:
1. The OE (output enable) signal is synchronized with the low level of the
LVDS_CLK and LVPECL_CLK signal.
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
CCI
/ V
CCO
V
IN
I
OUT
Tstore
θ
JA
Rating
V
CC
Pin Potential to Ground Pin
Input Voltage
DC Output Current
Storage Temperature
Package Thermal Resistance (Junction-to-Ambient)
With exposed pad soldered to GND
– Still-Air (multi-layer PCB)
– 200lfpm (multi-layer PCB)
– 500lfpm (multi-layer PCB)
Exposed pad
not
soldered to GND
– Still-Air (multi-layer PCB)
– 200lfpm (multi-layer PCB)
– 500lfpm (multi-layer PCB)
Value
–0.5 to +4.0
–0.5 to V
CCI
–50
–65 to +150
23
18
15
44
36
30
4.3
Unit
V
V
mA
°C
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
θ
JC
Package Thermal Resistance
(Junction-to-Case)
NOTE:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. This is a stress rating only and functional operation is not
implied at conditions other than those detailed in the operational sections of this data book. Exposure to ABSOLUTE MAXIMUM RATING conditions
for extended periods may affect device reliability.
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge
®
SY89825U
DC ELECTRICAL CHARACTERISTICS
Power Supply
T
A
= –40
°
C
Symbol
V
CCI,
V
CCO
I
CC
Parameter
Power Supply
(1)
Total Supply Current
(2)
Min.
2.37
—
Typ.
—
100
Max.
3.6
150
Min.
2.37
—
T
A
= +25
°
C
Typ.
—
100
Max.
3.8
150
Min.
2.37
—
T
A
= +85
°
C
Typ.
—
100
Max.
3.6
150
Unit
V
mA
Notes:
1. V
CCI
and V
CCO
must be connected together on the PCB such that they remain at the same potential. V
CCI
and V
CCO
are not internally connected on the die.
2. No load. Outputs floating.
LVDS Input
(V
CC
= 2.37V to 3.6V, GND = 0V)
T
A
= –40
°
C
Symbol
V
IN
V
ID
I
IL
R
IN
Parameter
Input Voltage Range
Differential Input Swing
Input Low Current
(1)
LVDS Differential Input Resistance
(LVDS_CLK to /LVDS_CLK)
Min.
0
100
–1.25
80
Typ.
—
—
—
100
Max.
2.4
—
—
120
Min.
0
100
–1.25
80
T
A
= +25
°
C
Typ.
—
—
—
100
Max.
2.4
—
—
120
Min.
0
100
–1.25
80
T
A
= +85
°
C
Typ.
—
—
—
100
Max.
2.4
—
—
120
Unit
V
mV
mA
Ω
Note:
1. For I
IL
, both LVDS inputs are grounded.
LVPECL Input/Output
(V
CC
= 2.37V to 3.6V, GND = 0V)
T
A
= –40
°
C
Symbol
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
I
IH
I
IL
Parameter
Input HIGH Voltage
(Single ended)
Input LOW Voltage
Minimum Input Swing
(1)
LVPECL_CLK
Common Mode Range
(2)
LVPECL_CLK
Output HIGH Voltage
(3)
Output LOW Voltage
(3)
Input HIGH Current
Input LOW Current
Min.
V
CC
– 1.165
V
CC
– 1.945
600
–1.5
Max.
V
CC
– 0.88
T
A
= +25
°
C
Min.
V
CC
– 1.165
Max.
V
CC
– 0.88
V
CC
– 1.625
—
–0.4
T
A
= +85
°
C
Min.
V
CC
– 1.165
V
CC
– 1.945
600
–1.5
Max.
V
CC
– 0.88
V
CC
– 1.625
—
–0.4
Unit
V
V
mV
V
V
V
µA
µA
V
CC
– 1.625 V
CC
– 1.945
—
–0.4
600
–1.5
V
CCO
– 1.085 V
CCO
– 0.880 V
CCO
– 1.025 V
CCO
– 0.880 V
CCO
– 1.025 V
CCO
– 0.880
V
CCO
– 1.830 V
CCO
– 1.555 V
CCO
– 1.810 V
CCO
– 1.620 V
CCO
– 1.810 V
CCO
– 1.620
—
0.5
150
—
—
0.5
150
—
—
0.5
150
—
Notes:
1. The V
PP
(min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay.
2. V
CMR
is defined as the range within which the V
IH
level may vary, with the device still meeting the propagation delay specification. The numbers in the table are
referenced to V
CCI
. The V
IL
level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to V
PP
(min.). The lower end of the
CMR range varies 1:1 with V
CCI
. The V
CMR
(min) will be fixed at 3.3V – |V
CMR
(min)|.
3. Outputs loaded with 50Ω to V
CC
-2V.
LVCMOS/LVTTL Control Inputs (OE, CLK_SEL)
(V
CC
= 2.37V to 3.6V, GND = 0V)
T
A
= –40
°
C
Symbol
V
IH
V
IL
I
IH
I
IL
Parameter
Input HIGH Voltage
Input LOW Voltage
Input HIGH Current
Input LOW Current
Min.
2.0
—
+20
—
Typ.
—
—
—
—
Max.
—
0.8
–250
–600
4
Min.
2.0
—
+20
—
T
A
= +25
°
C
Typ.
—
—
—
—
Max.
—
0.8
–250
–600
Min.
2.0
—
+20
—
T
A
= +85
°
C
Typ.
—
—
—
—
Max.
—
0.8
–250
–600
Unit
V
V
µA
µA
M9999-011907
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
Precision Edge
®
SY89825U
AC ELECTRICAL CHARACTERISTICS
(1)
V
CC
= 2.37V to 3.6V, GND = 0V
T
A
= –40
°
C
Symbol
f
MAX
t
PHL
t
PLH
t
SKEW
t
S(OE)
t
H(OE)
t
JITTER
Parameter
Max Toggle Frequency
(2)
Propagation Delay
(Differential)
(3)
LVPECL IN
LVDS IN
Within-Device Skew
(4)
Part-to-Part Skew
(5)
OE Set-Up Time
(6)
OE Hold Time
(6)
Random Jitter
(7)
Cycle-to-Cylce Jitter
(8)
Total Jitter
(9)
t
r
t
f
Output Rise/Fall Time
(20% – 80%)
Min.
2
0.600
0.800
—
—
1.0
0.5
—
—
—
300
—
Typ.
—
—
—
—
100
—
—
—
—
—
—
—
Max.
—
1.2
1.4
35
200
—
—
1
1
10
600
1.2
Min.
2
0.600
0.800
—
—
1.0
0.5
—
—
—
300
—
T
A
= +25
°
C
Typ.
—
0.900
1.1
20
100
—
—
—
—
—
450
—
Max.
—
1.2
1.4
35
200
—
—
1
1
10
600
1.2
2
0.600
0.800
—
—
1.0
0.5
—
—
—
300
—
T
A
= +85
°
C
Min.
Typ.
—
—
—
—
100
—
—
—
—
—
—
—
Max.
—
1.2
1.4
35
200
—
—
1
1
10
600
1.2
ps
ps
ns
ns
ps
(RMS)
ps
(RMS)
ps
(PP)
ps
ns
Unit
GHz
ns
t
(switchover)
Input Switchover
CLK_SEL-to-valid output
Notes:
1. Outputs loaded with 50Ω to V
CC
– 2V. Airflow
≥
300lfpm.
2. f
MAX
is defined as the maximum toggle frequency measured. Measured with a 750mV input signal, all loading with 50Ω to V
CC
–2V.
3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential
output signals.
4. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same
voltage and temperature.
5. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same
voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.
6. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,
set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures
outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.
7. Random jitter is measured using K28.7 pattern, measured at
≤
f
MAX
.
8. Cycle-to-cycle definition: the variation of periods between adjacent cycles, Tn–Tn-1 where T is the time between rising edges of the output signal.
9. Total jitter definition: with an ideal clock input of frequency
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